The technology disclosed relates to granular analysis of design data used to prepare chip designs for manufacturing and to identification of similarities and differences among parts of design data files. In particular, it relates to parsing data and organizing into canonical forms, digesting the canonical forms, and comparing digests of design data from different sources, such as designs and libraries of design templates. Organizing the design data into canonical forms generally reduces the sensitivity of data analysis to variations in data that have no functional impact on the design. The details of the granular analysis vary among design languages used to represent aspects of a design. For various design languages, granular analysis includes partitioning design files by header/cell portions, by separate handling of comments, by functionally significant/non-significant data, by whitespace/non-whitespace, and by layer within a unit of design data. The similarities and differences of interest depend on the purpose of the granular analysis. The comparisons are useful in many ways.

Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow

Some embodiments provide a system that provides design rule checking in an electronic design automation (EDA) application. During operation, the system detects a change to a schematic by a user of the EDA application. Next, the system automatically applies a set of dynamic design rules to the schematic upon detecting the change. Finally, the system notifies the user of a rule violation if the schematic violates one or more of the dynamic design rules. The system allows the user to specify which dynamic rules to apply when the user is modifying the schematic.

Dynamic rule checking in electronic design automation

Network-based system and method for providing custom circuits to customers. At least one computer may be used to perform the method. A specification of a custom circuit may be received from at least one first user over a wide area network. The specification may specify a design of the custom circuit. Information regarding the custom circuit may be provided on a website over the wide area network. At least one purchase order of the custom circuit may be received from at least one second user over the wide area network. The purchase order(s) may include delivery information for the custom circuit. Delivery of the custom circuit may be configured based on the purchase order(s). The first user(s) may receive payment based on the purchase order(s).

Online Custom Circuit Marketplace

User interface layout is defined using constraints on the position and size of visual elements. Constraints may be explicit and/or implicit. Interactive design code helps designers create constraints without conflict or redundancy. The design code determines whether a proposed layout constraint is incompatible with established constraints, receives a designer's selection of an incompatible constraint, and displays user interface elements in previews of alternate layouts having different constraints. A designer can interactively explore possible resolutions of constraint incompatibilities as soon as the constraints are detectable. The design code animates a transition between possible layouts, highlights the incompatible constraints, and hides the compatible constraints. A subset of constraints may be shown, such as only the recently added constraints and closely related constraints.

Display and Resolution of Incompatible Layout Constraints

When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer.

Design-Rule-Check Waiver

Techniques for incrementally analyzing layout design data are disclose. With various implementations, a subsequent incremental analysis can be made for only portions of layout design data, using a subset of available analysis criteria, or some combination of both. For example, the analysis can be limited to errors identified in a previous analysis process, to changes in the layout design data made after a previous analysis process, to particular areas specified by a designer, or some combination thereof. Still further, the analysis process may be performed using only a subset of analysis criteria relevant to the portions of the design data being analyzed, a subset of the initial analysis criteria that the design data failed in a previous analysis process, a subset of the initial analysis criteria selected by the designer, or some combination thereof. Further, such an incremental analysis process can be initiated before a previous analysis process has completed.

Incremental Layout Analysis

At 65 nm and below, parametric yield loss has become the predominant yield-limiting factor, making the analysis and optimization of electrical performance crucial to market success. Until now, however, the full efficacy of electrical design for manufacturing (EDFM) tools has been limited by the separation of detailed physical layout information from both detailed knowledge of design intent and the logical circuits implemented by the layout. We introduce a Logic-Driven Layout Framework that provides EDFM tools with unified access to all types of design data (physical, logical, electrical) in a single environment, enabling circuit designers to quickly identify and debug potential parametric issues, and, without losing domain context, share their findings with designers working in different design domains (logic, layout, manufacturing, etc.).

Unifying design data during verification: Implementing Logic-Driven Layout analysis and debug

Described herein are methods for generating concise descriptions of an IC layout. The description from a first format is read and deciphered for determining any patterns in any repetition of elements of an IC layout. The repetitions are then expressed in a concise form to further compress the description. Duplicative information can be avoided by the use of these methods and systems. The repetition patterns described include row-type and column-type patterns. Some selected element instances may be described as part of a random-type arrangement of element instances instead of being described individually.

Anant Adke

Papers

Incremental Layout Analysis

Unifying design data during verification: Implementing Logic-Driven Layout analysis and debug

Compressing integrated circuit design data files