A wireless telecommunication system comprises base stations for communicating with terminal devices. One or more base stations support a power boost operating mode in which a base station's available transmission power is concentrated in a subset of its available transmission resources to provide enhanced transmission powers as compared to transmission powers on these transmission resources when the base station is not operating in the power boost mode. A base station establishes an extent to which one or more base stations in the wireless telecommunications system support the power boost operating mode conveys an indication of this to a terminal device. The terminal device receives the indication and uses the corresponding information to control its acquisition of a base station of the wireless telecommunication system, for example by taking account of which base stations support power boosting and/or when power boosting is supported during a cell attach procedure.

Telecommunications apparatus and methods

Part I. Silicon Photonics - Introduction: 1. Fabless Silicon Photonics: 1.1 Introduction 1.2 Silicon photonics - the next fabless semiconductor industry 1.3 Applications 1.4 Technical challenges and the state of the art 1.5 Opportunities 2. Modelling and Design Approaches: 2.1 Optical Waveguide Mode Solver 2.2 Wave Propagation 2.3 Optoelectronic models 2.4 Microwave Modelling 2.5 Thermal Modelling 2.6 Photonic Circuit Modelling 2.7 Physical Layout 2.8 Software Tools Integration Part II. Silicon Photonics - Passive Components: 3. Optical Materials and Waveguides: 3.1 Silicon-on-Insulator 3.2 Waveguides 3.3 Bent waveguides 3.4 Code Listings 3.5 Problems 4. Fundamental Building Blocks: 4.1 Directional couplers 4.2 Y-Branch 4.3 Mach-Zehnder Interferometer 4.4 Ring resonators 4.5 Waveguide Bragg Grating Filters 4.6 Code Listings 4.7 Problems 5. Optical I/O: 5.1 The challenge of optical coupling to silicon photonic chips 5.2 Grating Coupler 5.3 Edge Coupler 5.4 Polarization 5.5 Code Listings 5.6 Problems Part III. Silicon Photonics - Active Components: 6. Modulators: 6.1 Plasma Dispersion E 6.2 PN Junction Phase Shifter 6.3 Micro-ring Modulators 6.4 Forward-biased PIN Junction 6.5 Active Tuning 6.6 Thermo-Optic Switch 6.7 Code Listings 6.8 Problems 7. Detectors: 7.1 Performance Parameters 7.2 Fabrication 7.3 Types of detectors 7.4 Design Considerations 7.5 Detector modelling 7.5.2 Electronic Simulations 7.6 Code Listings 7.7 Problems 8. Lasers: 8.1 External Lasers 8.2 Laser Modelling 8.3 Co-Packaging 8.4 Hybrid Silicon Lasers 8.5 Monolithic Lasers 8.6 Alternative Light Sources 8.7 Problems Part IV. Silicon Photonics - System Design: 9. Photonic Circuit Modelling: 9.1 Need for photonic circuit modelling 9.2 Components for System Design 9.3 Compact Models 9.4 Directional Coupler - Compact Model 9.5 Ring Modulator - Circuit Model 9.6 Grating Coupler - S Parameters 9.7 Code Listings 10. Tools and Techniques: 10.1 Process Design Kit (PDK) 10.2 Mask Layout 11. Fabrication: 11.1 Fabrication Non-Uniformity 11.2 Problems 12. Testing and Packaging: 12.1 Electrical and Optical Interfacing 12.2 Automated Optical Probe Stations 12.3 Design for Test 13. Silicon Photonic System Example: 13.1 Wavelength Division Multiplexed Transmitter.

Silicon Photonics Design: From Devices to Systems

Silicon Photonics technology is rapidly maturing as a platform for larger-scale photonic circuits. As a result, the associated design methodologies are also evolving from componentoriented design to a more circuit-oriented design flow, that makes abstraction from the very detailed geometry and enables design on a larger scale. In this paper, we review the state of this emerging photonic circuit design flow and its synergies with electronic design automation (EDA). We cover the design flow from schematic capture, circuit simulation, layout and verification. We discuss the similarities and the differences between photonic and electronic design, and the challenges and opportunities that present themselves in the new photonic design landscape, such as variability analysis, photonic-electronic co-simulation and compact model definition. Silicon Photonics Circuit Design: Methods, Tools and

https://www.onlinelibrary.wiley.com/doi/epdf/10.1002/lpor.201700237

Silicon Photonics Circuit Design: Methods, Tools and Challenges

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

We demonstrate fully-etched fiber-waveguide grating couplers with sub-wavelength gratings showing high coupling efficiency as well as low back reflections for both transverse electric (TE) and transverse magnetic (TM) modes. The power reflection coefficients for the TE and TM modes have been significantly suppressed to -16.2 dB and -20.8 dB, respectively. Focusing grating lines have also been used to reduce the footprint of the design. Our sub-wavelength grating couplers for the TE and TM modes show respective measured insertion losses of 4.1 dB and 3.7 dB with 1-dB bandwidths of 30.6 nm (3-dB bandwidth of 52.3 nm) and 47.5 nm (3-dB bandwidth of 81.5 nm), respectively.

Focusing sub-wavelength grating couplers with low back reflections for rapid prototyping of silicon photonic circuits

Techniques are disclosed for modifying an existing micro-device design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design (Figure 4). The associated design data then is identified and provided to the micro-device designer, who may choose to modify the design based upon the manufacturing criteria (Figure 5A). In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the micro-device (Figure 5B).

Design for manufacturability

Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.

Secure exchange of information in electronic design automation

Systems and methods for verifying integrated circuit designs: (a) receive input corresponding to physical layouts of cells of the design and available master cells. The systems and methods then determine if the design cells are intended to correspond to one of the master cells, and if so, the systems and methods then determine if the layouts of the cells and the corresponding master cells match one another, e.g., by a layout vs. layout comparison of the design cell with the master cell to determine if the coordinates of the polygon(s) in the design cell match corresponding coordinates of the polygon(s) in the master cell. An “XOR” comparison may be used to determine if the design cell features match the corresponding master cell features. Computer-readable media may be adapted to include computer-executable instructions for performing such methods and operating such systems.

In-line XOR checking of master cells during integrated circuit design rule checking

This paper describes design methodologies developed for silicon photonics integrated circuits. The approach presented is inspired by methods employed in the Electronics Design Automation (EDA) community. This is complemented by well established photonic component design tools, compact model synthesis, and optical circuit modelling. A generic silicon photonics design kit, as described here, is available for download at http://www.siepic.ubc.ca/GSiP.

Design methodologies for silicon photonic integrated circuits

A defect identification tool is disclosed that predicts locations at which defects in a microdevice are most likely to occur (Fig. 6, n601). The tool may identify both a type of defect and the particular netlists in which that defect is likely to occur (Fig. 6, n603). A test circuit generation tool can then subsequently use this defect information to generate a test circuit that tests for the defect in the identified portions of the microcircuit (Fig. 6, n619). Similarly, an automatic test pattern generation tool may use the defect location information to generate test data custom-tailored to check for faults corresponding to the identified defect in the specified portions of the microcircuit. Various implementations of the tool may be used both to identify the locations at which defects caused by systematic errors, such as manufacturing process deficiencies or flaws, are most likely to occur and the locations at which randomly-created defects are most likely to occur.

John G. Ferguson

Papers

Design for manufacturability

Secure exchange of information in electronic design automation

In-line XOR checking of master cells during integrated circuit design rule checking

Design methodologies for silicon photonic integrated circuits

Defect location identification for microdevice manufacturing and test