We are at the beginning of a genomic revolution in which all known species are planned to be sequenced. Accessing such data for comparative analyses is crucial in this new age of data-driven biology. Here, we introduce an improved version of DIAMOND that greatly exceeds previous search performances and harnesses supercomputing to perform tree-of-life scale protein alignments in hours, while matching the sensitivity of the gold standard BLASTP.

/pdf/sensitive-protein-alignments-at-tree-of-life-scale-using-5fll2866w4.pdf

Sensitive protein alignments at tree-of-life scale using DIAMOND.

In-memory tree structured index search is a fundamental database operation. Modern processors provide tremendous computing power by integrating multiple cores, each with wide vector units. There has been much work to exploit modern processor architectures for database primitives like scan, sort, join and aggregation. However, unlike other primitives, tree search presents significant challenges due to irregular and unpredictable data accesses in tree traversal. In this paper, we present FAST, an extremely fast architecture sensitive layout of the index tree. FAST is a binary tree logically organized to optimize for architecture features like page size, cache line size, and SIMD width of the underlying hardware. FAST eliminates impact of memory latency, and exploits thread-level and datalevel parallelism on both CPUs and GPUs to achieve 50 million (CPU) and 85 million (GPU) queries per second, 5X (CPU) and 1.7X (GPU) faster than the best previously reported performance on the same architectures. FAST supports efficient bulk updates by rebuilding index trees in less than 0.1 seconds for datasets as large as 64Mkeys and naturally integrates compression techniques, overcoming the memory bandwidth bottleneck and achieving a 6X performance improvement over uncompressed index search for large keys on CPUs.

/pdf/fast-fast-architecture-sensitive-tree-search-on-modern-cpus-4b5678kmdm.pdf

FAST: fast architecture sensitive tree search on modern CPUs and GPUs

Prior work has shown dramatic acceleration for various database operations on GPUs, but only using primitives that are not part of conventional database languages such as SQL. This paper implements a subset of the SQLite command processor directly on the GPU. This dramatically reduces the effort required to achieve GPU acceleration by avoiding the need for database programmers to use new programming languages such as CUDA or modify their programs to use non-SQL libraries. This paper focuses on accelerating SELECT queries and describes the considerations in an efficient GPU implementation of the SQLite command processor. Results on an NVIDIA Tesla C1060 achieve speedups of 20-70X depending on the size of the result set.

/pdf/accelerating-sql-database-operations-on-a-gpu-with-cuda-5ckiz7v0i4.pdf

Accelerating SQL database operations on a GPU with CUDA

The focus of this paper is on investigating efficient hash join algorithms for modern multi-core processors in main memory environments. This paper dissects each internal phase of a typical hash join algorithm and considers different alternatives for implementing each phase, producing a family of hash join algorithms. Then, we implement these main memory algorithms on two radically different modern multi-processor systems, and carefully examine the factors that impact the performance of each method.Our analysis reveals some interesting results -- a very simple hash join algorithm is very competitive to the other more complex methods. This simple join algorithm builds a shared hash table and does not partition the input relations. Its simplicity implies that it requires fewer parameter settings, thereby making it far easier for query optimizers and execution engines to use it in practice. Furthermore, the performance of this simple algorithm improves dramatically as the skew in the input data increases, and it quickly starts to outperform all other algorithms.

/pdf/design-and-evaluation-of-main-memory-hash-join-algorithms-4gct9enwg3.pdf

Design and evaluation of main memory hash join algorithms for multi-core CPUs

The architectural changes introduced with multi-core CPUs have triggered a redesign of main-memory join algorithms. In the last few years, two diverging views have appeared. One approach advocates careful tailoring of the algorithm to the architectural parameters (cache sizes, TLB, and memory bandwidth). The other approach argues that modern hardware is good enough at hiding cache and TLB miss latencies and, consequently, the careful tailoring can be omitted without sacrificing performance. In this paper we demonstrate through experimental analysis of different algorithms and architectures that hardware still matters. Join algorithms that are hardware conscious perform better than hardware-oblivious approaches. The analysis and comparisons in the paper show that many of the claims regarding the behavior of join algorithms that have appeared in literature are due to selection effects (relative table sizes, tuple sizes, the underlying architecture, using sorted data, etc.) and are not supported by experiments run under different parameters settings. Through the analysis, we shed light on how modern hardware affects the implementation of data operators and provide the fastest implementation of radix join to date, reaching close to 200 million tuples per second.

/pdf/main-memory-hash-joins-on-multi-core-cpus-tuning-to-the-3gwmh3t1g1.pdf

Main-memory hash joins on multi-core CPUs: Tuning to the underlying hardware

Join is an important database operation. As computer architectures evolve, the best join algorithm may change hand. This paper re-examines two popular join algorithms -- hash join and sort-merge join -- to determine if the latest computer architecture trends shift the tide that has favored hash join for many years. For a fair comparison, we implemented the most optimized parallel version of both algorithms on the latest Intel Core i7 platform. Both implementations scale well with the number of cores in the system and take advantages of latest processor features for performance. Our hash-based implementation achieves more than 100M tuples per second which is 17X faster than the best reported performance on CPUs and 8X faster than that reported for GPUs. Moreover, the performance of our hash join implementation is consistent over a wide range of input data sizes from 64K to 128M tuples and is not affected by data skew. We compare this implementation to our highly optimized sort-based implementation that achieves 47M to 80M tuples per second. We developed analytical models to study how both algorithms would scale with upcoming processor architecture trends. Our analysis projects that current architectural trends of wider SIMD, more cores, and smaller memory bandwidth per core imply better scalability potential for sort-merge join. Consequently, sort-merge join is likely to outperform hash join on upcoming chip multiprocessors. In summary, we offer multicore implementations of hash join and sort-merge join which consistently outperform all previously reported results. We further conclude that the tide that favors the hash join algorithm has not changed yet, but the change is just around the corner.

/pdf/sort-vs-hash-revisited-fast-join-implementation-on-modern-1kp6w7lc0r.pdf

Sort vs. Hash revisited: fast join implementation on modern multi-core CPUs

Recent approaches exploiting the massively parallel architecture of graphics processors (GPUs) to accelerate database operations have achieved intriguing results. While parallel sorting received significant attention, parallel search has not been explored. With p-ary search we present a novel parallel search algorithm for large-scale database index operations that scales with the number of processors and outperforms traditional thread-level parallel GPU and CPU implementations. With parallel architectures becoming omnipresent, and with searching being a fundamental functionality for many applications, we expect it to be applicable beyond the database domain. While GPUs do not appear to be ready to be adopted for general-purpose database applications yet, given their rapid development, we expect this to change in the near future. The trend towards massively parallel architectures, combining CPU and GPU processing, encourages development of parallel techniques on both architectures.

/pdf/parallel-search-on-video-cards-68obgc7ilw.pdf

Parallel search on video cards

Hopfield neural networks are often used to solve difficult combinatorial optimization problems. Multiple restarts versions find better solutions but are slow on serial computers. Here, we study two parallel implementations on SIMD computers of multiple restarts Hopfield networks for solving the maximum clique problem. The first one is a fine-grained implementation on the Kestrel Parallel Processor, a linear SIMD array designed and built the University of California, Santa Cruz. The second one is an implementation on the MasPar MP-2 according to the ''SIMD Phase Programming Model'', a new method to solve asynchronous, irregular problems on SIMD machines. We find that the neural networks map well to the parallel architectures and afford substantial speedups with respect to the serial program, without sacrificing solution quality.

Optimizing neural networks on SIMD parallel computers

Background

The morphometric analysis of red blood cells (RBCs) is an important area of study and has been performed previously for fixed samples. We present a novel method for the analysis of morphologic changes of live erythrocytes as a function of time. We use this method to extract information on alkaline hemolysis fragility. Many other toxins lyse cells by membrane poration, which has been studied by averaging over cell populations. However, no quantitative data are available for changes in the morphology of individual cells during membrane poration-driven hemolysis or for the relation between cell shape and fragility.



Methods

Hydroxide, a porating agent, was generated in a microfluidic enclosure containing RBCs in suspension. Automatic cell recognition, tracking, and morphometric measurements were done by using a custom image analysis program. Cell area and circular shape factor (CSF) were measured over time for individual cells. Implementations were developed in MATLAB and on Kestrel, a parallel computer that affords higher speed that approaches real-time processing.



Results

The average CSF went through a first period of fast increase, corresponding to the conversion of discocytes to spherocytes under internal osmotic pressure, followed by another period of slow increase until the fast lysis event. For individual cells, the initial CSF was shown to be inversely correlated to cell lifetime (linear regression factor R = 0.44), with discocytes surviving longer than spherocytes. The inflated cell surface area to volume ratio was also inversely correlated to lifetime (R = 0.43) but not correlated to the CSF. Lifetime correlated best to the ratio of cell inflation volume (Vfinal − Vinitial) to surface area (R = 0.65).



Conclusions

RBCs inflate at a rate proportional to their surface area, in agreement with a constant flux model, and lyse after attaining a spherical morphology. Spherical RBCs display increased alkaline hemolysis fragility (shorter lifetimes), providing an explanation for the increased osmotic fragility of RBCs from patients who have spherocytosis. © 2005 Wiley-Liss, Inc.

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cyto.a.20135

Alkaline hemolysis fragility is dependent on cell shape: results from a morphology tracker.

Publisher Summary This chapter introduces P-ary search the scalable parallel search algorithm that uses single instruction multiple data architectures—graphical processing unit (GPUs). The increases in memory bandwidth over the past decade are a result of the multi/many-core era, with GPUs being a poster child, offering memory bandwidth well in excess of 100 GB/s. However, achieving peak bandwidth requires concurrent (parallel) memory access from all cores. The obvious use of increasingly parallel architectures for large-scale search applications is to execute multiple search queries simultaneously, which often results in significant increases in throughput. Query response time, on the other hand, remains memory-latency bound, unless one abandons conventional serial algorithms and goes back to the drawing board. To grasp the implications of porting a memory-bound application like search to the GPU, this chapter first conducts a brief memory performance analysis. Conventional threading models and the memory access pattern produced by concurrent search queries do not map well to the GPU's memory subsystem. With P-ary search it demonstrates how parallel memory access combined with the superior synchronization capabilities of SIMD architectures like GPUs can be leveraged to compensate for memory latency. P-ary search outperforms conventional search algorithms not only in terms of throughput but also response time. Implemented on a GPU it can outperform a similarly priced CPU by up to three times, and is compatible with existing index data structures like inverted lists and B-trees.

Andrea Di Blas

Papers

Sort vs. Hash revisited: fast join implementation on modern multi-core CPUs

Parallel search on video cards

Optimizing neural networks on SIMD parallel computers

Alkaline hemolysis fragility is dependent on cell shape: results from a morphology tracker.

Large-Scale GPU Search