A modular rearview mirror assembly for vehicles incorporates a housing into the mirror assembly case for supporting an electronic control module to reduce the vibration, to ease the installation of the components in the mirror assembly, and to improve access to the various components in the mirror assembly for maintenance or repair. The rearview mirror assembly includes a reflective element, at least one electrical component mounted to the reflective element, and a case housing the reflective element and the electrical component. An electronic control module is supported by the case which communicates with the electrical component. Preferably, the electronic control module is supported by a housing that is either molded with the case or welded to the inner surface of the case to support the electronic control module independently from the electrical component.

Modular rearview mirror assembly including an electronic control module

An integrated circuit includes a test port operating at a first clock speed and at least one functional logic block operating at a second clock speed which is faster than the first clock speed. A control register, formed by boundary scan cells, operates at the first clock speed and provides control inputs to the functional block to control emulation tasks. The control register is writable via a serial shift operation through the test port while the functional block is operating. The outputs of the control register which are being provided to the functional block are held constant during the serial shift operation. An observation register, formed by boundary scan cells, operates at the first clock speed, and is readable through the test port via a serial shift operation, while the functional block is operating. The observation register receives signals from the functional block indicating status of the functional block.

Low cost emulation scheme implemented via clock control using JTAG controller in a scan environment

A system and method for architecting design for test circuitry (eg, scan architecting) within an integrated circuit design having subdesigns (eg, modules) The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (eg, top level scan chains) The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc), properties of a particular scan chain (membership, name, etc), test signals (scan-in, scan-out, scan-enable, etc), complex elements used as part of a scan chain without requiring scan replacement, wires and latches forming connections between scan elements; this information is associated with the selected design database Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (eg specified) scan elements During analysis, the logic within the design database is not altered and a script is generated for user modification/verification Specification and analysis can be executed iteratively until the desired scan structures are planned Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis

Hierarchical scan architecture for design for test applications

A plug-in JTAG test card (200) includes JTAG boundary scan circuitry (230) which may be used to drive JTAG test data out onto portions of buses (170, 195) connected to peripheral slots (160, 180, 190). One or more of the JTAG plug-in test cards (200) can be used to verify the integrity of each of the point-to-point connections on the buses (170, 195) which terminate in the peripheral plug-in slots. In one advantageous embodiment, the plug-in JTAG test cards (200) simulate a dual in-line memory module (DIMM) or single in-line memory module (SIMM) cards which include scan test buffer circuitry (230) but do not actually include memory chip so that an inexpensive plug-in card (200) can be used to provide JTAG testing at the manufacturing level for multiple motherboards (600). In a particularly preferred embodiment, JTAG boundary scan buffer circuits (230), such as, for example, SN74ABT8245's, are used as test circuits rather than for their intended use as interface circuits.

Jtag testing of buses using plug-in cards with jtag logic mounted thereon

A method and apparatus provides an analog mode of operation of a standard test access bus interface based on a standard boundary scan architecture which is limited to use of digital signals. Circuits are included in the interface which enable the sharing of control paths at separate time intervals defined under instruction control for processing analog and digital signals thereby providing a hybrid capability without any increase in the number of lines required by the interface.

Boundary scan architecture analog extension with direct connections

Disclosed is a test method and system for boundary testing a circuit network. The network, made up of individual integrated circuit chips mounted on a printed circuit card or board, has at least one integrated circuit that is testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit that is testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing. The test system has a test access port interface with a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O. The test access port also has an instruction register, a bypass register, a test clock generator, and a Level Sensitive Scan Device boundary scan register.

System and method for testing a circuit network having elements testable by different boundary scan standards

A method and system are provided for improved communication between devices. A first device having an associated first clock rate may communicate with a second device having an associated second clock rate. Particular periods of time are determined during which metastability may occur as a result of differences between the first clock rate and the second clock rate. Data transmitted from the first device to the second device is continually processed. During those particular periods of time when metastability may occur, the processed data is input into the second device. During all other periods of time, the data is input directly into the second device.

Method and system for reduced metastability between devices which communicate and operate at different clock frequencies

This paper performs a detailed evaluation of a fault-tolerant distributed broadcasting algorithm for cube connected networks. The main areas of evaluation are the following: (1) Algorithm effectiveness in the presence of multiple faults, (2) Establishing the maximum number of link faults allowed, before the algorithm fails to guarantee 100% effectiveness. The evaluation was done to networks connected in 3-, 4-, 5-, and 6-cube configurations. The results of the simulation were analyzed to establish algorithm characteristics under multiple faults.

/pdf/evaluation-of-a-fault-tolerant-distributed-broadcast-1dt2yjjwih.pdf

Andres M. Molina

Papers

System and method for testing a circuit network having elements testable by different boundary scan standards

Method and system for reduced metastability between devices which communicate and operate at different clock frequencies

Evaluation of a fault tolerant distributed broadcast algorithm in hypercube multicomputers