A device for introducing a rotatable atherectomy catheter into an artery of a patient comprises an elongated hollow introducer sheath attached to the distal end of a housing formed with a bore in which is mounted a seal. The seal is formed with an expandable opening to selectively prevent fluid flow through the seal. The seal includes a plurality of penetrable disks serially mounted in the bore. A permutation of slits and holes in the disks provides an assembled relationship allowing penetration of the seal by a catheter, while also preventing fluid leakage from the seal. The device includes a seal expander and a rear connector. The seal expander is engageable with the housing attached to the sheath, and the connector is engageable with the expander. The expander provides an insertion tube for penetrating the seal which expands to form a fluid tight seal around the insertion tube. The connector provides a second seal for preventing fluid leakage from the connector during operation of the rotatable catheter.

Introducer sheath with seal protector

Circuits (Fig. 1) that operate with power supplies (VDD) of less than 1 Volt are present. More particularly, circuits (Fig. 1) that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (M1A, M1B) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor (MOS) to bipolar junction transistors may implement the techniques presented herein.

Low voltage operational transconductance amplifier circuits

This paper presents a precision 18-bit 12.5 MS/s ADC that was designed primarily for digital X-ray imaging systems. This ADC was intended to have a faster output data rate than the precision successive approximation ADCs normally chosen for these systems but with similar DC accuracy and dynamic range. The chosen architecture consists of a pipeline of two multi-bit successive approximation converters. The first successive approximation ADC generates an initial coarse conversion result. The DACs within this converter are then used to generate a residue which is amplified by a residue amplifier before being converted by a second successive approximation ADC. Four comparators within each ADC allow 2 bits to be determined each bit trial. Capacitor mismatch errors are digitally corrected with error coefficients stored in non-volatile memory. Dither is used to reduce the effect of errors in the flash ADC within the second ADC. The ADC was implemented on 0.25 m CMOS process with PIP capacitors and achieves a SNR of 93 dB with a 50 kHz input tone. INL and DNL are within LSB and LSB respectively. Power consumption is 105 mW, excluding LVDS interface power.

An 18 b 12.5 MS/s ADC With 93 dB SNR

A circuit for analog-to-digital conversion is disclosed comprising multiplexed ADCs. Dithering is introduced into the circuit before conversion and subtracted out of the resulting digital output stream. Gain control feedback loops are employed to eliminate non-unity gain error of the dither signal and multiplexed ADC differential gain errors. Correlation between the digital output stream and the dither signal is used to detect a non-unity condition and derive gain control feedback. Correlation with the dither signal is also used to detect gain differences between multiplexed ADCs and generate corrective feedback.

Combined and simplified multiplexing and dithered analog to digital converter

An analog-to-digital converter having error correction in the digital stages of the converter. A calibration microprocessor executes a correction value program prior to, or interspaced with, the normal operation of the converter. From either of two calibration programs, appropriate digital correction values are stored into a digital memory. The analog input signal is converted to a digital signal by a main range analog-to-digital converter, with the output of the converter addressing the memory containing the error correction values. The main range digital value is reconverted to an analog signal which is compared to the original input signal to determine the difference therebetween. This analog difference is converted to a digital signal and combined with the main range digital signal and the addressed correction values to produce the digital output signal of the conversion system.

Subranging analog-to-digital converter with digital error correction

A microprocessor-compatible, 14-bit, 10- mu s subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated. >

A 14-bit 10- mu s subranging A/D converter with S/H

A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-­sources of a DAC. The flash converter input circuit com­prises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-­sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-­current sources is an overlap bit having the same current weighting as the LSB of the preceding group. Setting of the overlap bit makes it possible to develop a correct output for the DAC for each of the 2nd through 4th cycles without altering bits already determined in previous cycles. The converter provides an optional 5th cycle making possi­ble a 14-bit output or an increased yield of 12-bit con­verters.

Sub-ranging a/d converter with flash converter having balanced input

A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter (34) the output of which sets the latches for corresponding bit-current-sources (92) of a DAC (32). The flash converter input circuit comprises identical residue and reference amplifiers (18, 18A) driving symmetrical residue and reference networks for controlling the flash converter comparators (56). The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group. Setting of the overlap bit makes it possible to develop a correct output for the DAC for each of the 2nd through 4th cycles without altering bits already determined in previous cycles. The converter provides an optional 15th cycle making possible a 14-bit output or an increased yield of 12-bit converters.

Andrew Martin Mallinson

Papers

A 14-bit 10- mu s subranging A/D converter with S/H

Sub-ranging a/d converter with flash converter having balanced input

Sub-ranging A/D converter with improved error correction