International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. 

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. 

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.




* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Three-Dimensional Integrated Circuit Design

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

Although transistor density continues to increase, voltage scaling has stalled and thus power density is increasing each technology generation. Particularly in mobile devices, which have limited cooling options, these trends lead to a utilization wall in which sustained chip performance is limited primarily by power rather than area. However, many mobile applications do not demand sustained performance; rather they comprise short bursts of computation in response to sporadic user activity. To improve responsiveness for such applications, this paper explores activating otherwise powered-down cores for sub-second bursts of intense parallel computation. The approach exploits the concept of computational sprinting, in which a chip temporarily exceeds its sustainable thermal power budget to provide instantaneous throughput, after which the chip must return to nominal operation to cool down. To demonstrate the feasibility of this approach, we analyze the thermal and electrical characteristics of a smart-phone-like system that nominally operates a single core (~1W peak), but can sprint with up to 16 cores for hundreds of milliseconds. We describe a thermal design that incorporates phase-change materials to provide thermal capacitance to enable such sprints. We analyze image recognition kernels to show that parallel sprinting has the potential to achieve the task response time of a 16W chip within the thermal constraints of a 1W mobile platform.

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Computational sprinting

Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Integrated Circuit Devices and Methods and Apparatuses for Designing Integrated Circuit Devices

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this second edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

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Power Distribution Networks with On-Chip Decoupling Capacitors

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.

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Scaling trends of on-chip power distribution noise

1. Introduction.- 1.1 Evolution of integrated circuit technology.- 1.2 Evolution of design objectives.- 1.3 The problem of power distribution.- 1.4 Deleterious effects of power distribution noise.- 1.4.1 Signal delay uncertainty.- 1.4.2 On-chip clock jitter.- 1.4.3 Noise margin degradation.- 1.4.4 Degradation of gate oxide reliability.- 1.5 Book outline.- 2. Inductive Properties of Electric Circuits.- 2.1 Definitions of inductance.- 2.1.1 Field energy definition.- 2.1.2 Magnetic flux definition.- 2.1.3 Partial inductance.- 2.1.4 Net inductance.- 2.2 Variation of inductance with frequency.- 2.2.1 Uniform current density approximation.- 2.2.2 Inductance variation mechanisms.- 2.2.3 Simple circuit model.- 2.3 Inductive behavior of circuits.- 2.4 Inductive properties of on-chip interconnect.- 2.5 Summary.- 3. Properties of On-Chip Inductive Current Loops.- 3.1 Introduction.- 3.2 Dependence of inductance on line length.- 3.3 Inductive coupling between two parallel loop segments.- 3.4 Application to circuit analysis.- 3.5 Summary.- 4. Electromigration.- 4.1 Physical mechanism of electromigration.- 4.2 Electromigration-induced mechanical stress.- 4.3 Steady state limit of electromigration damage.- 4.4 Dependence of electromigration lifetime on the line dimensions.- 4.5 Statistical distribution of electromigration lifetime.- 4.6 Electromigration lifetime under AC current.- 4.7 Electromigration in novel interconnect technologies.- 4.8 Designing for electromigration reliability.- 4.9 Summary.- 5. High Performance Power Distribution Systems.- 5.1 Physical structure of a power distribution system.- 5.2 Circuit model of a power distribution system.- 5.3 Output impedance of a power distribution system.- 5.4 A power distribution system with a decoupling capacitor.- 5.4.1 Impedance characteristics.- 5.4.2 Limitations of a single-tier decoupling scheme.- 5.5 Hierarchical placement of decoupling capacitance.- 5.6 Resonance in power distribution networks.- 5.7 Full impedance compensation.- 5.8 Case study.- 5.9 Design considerations.- 5.9.1 Inductance of the decoupling capacitors.- 5.9.2 Interconnect inductance.- 5.10 Limitations of the one-dimensional circuit model.- 5.11 Summary.- 6. On-Chip Power Distribution Networks.- 6.1 Styles of on-chip power distribution networks.- 6.1.1 Basic structure of on-chip power distribution networks.- 6.1.2 Improving the impedance characteristics of on-chip power distribution networks.- 6.1.3 Evolution of power distribution networks in Alpha microprocessors.- 6.2 Allocation of on-chip decoupling capacitance.- 6.2.1 Types of on-chip decoupling capacitance.- 6.2.2 Allocation strategies.- 6.2.3 On-chip switching voltage regulator.- 6.3 Die-package interface.- 6.4 Other considerations.- 6.5 Summary.- 7. Computer-Aided Design and Analysis.- 7.1 Design flow for on-chip power distribution networks.- 7.2 Linear analysis of power distribution networks.- 7.3 Modeling power distribution networks.- 7.4 Characterizing the power current requirements of on-chip circuits.- 7.5 Numerical methods for analyzing power distribution networks.- 7.6 Summary.- 8. Inductive Properties of On-Chip Power Distribution Grids.- 8.1 Power transmission circuit.- 8.2 Simulation setup.- 8.3 Grid types.- 8.4 Inductance versus line width.- 8.5 Dependence of inductance on grid type.- 8.5.1 Non-interdigitated versus interdigitated grids.- 8.5.2 Paired versus interdigitated grids.- 8.6 Dependence of Inductance on grid dimensions.- 8.6.1 Dependence of inductance on grid width.- 8.6.2 Dependence of inductance on grid length.- 8.6.3 Sheet inductance of power grids.- 8.6.4 Efficient computation of grid inductance.- 8.7 Summary.- 9. Variation of Grid Inductance with Frequency.- 9.1 Analysis approach.- 9.2 Discussion of inductance variation.- 9.2.1 Circuit models.- 9.2.2 Analysis of inductance variation.- 9.3 Summary.- 10. Inductance/Area/Resistance Tradeoffs.- 10.1 Inductance vs. resistance tradeoff under a constant grid area constraint.- 10.2 Inductance vs. area tradeoff under a constant grid resistance constraint.- 10.3 Summary.- 11. Scaling Trends Of On-Chip Power Distribution Noise.- 11.1 Prior work.- 11.2 Interconnect characteristics.- 11.2.1 Global interconnect characteristics.- 11.2.2 Scaling of the grid inductance.- 11.2.3 Flip-chip packaging characteristics.- 11.2.4 Impact of on-chip capacitance.- 11.3 Model of power supply noise.- 11.4 Power supply noise scaling.- 11.4.1 Analysis of constant metal thickness scenario.- 11.4.2 Analysis of the scaled metal thickness scenario.- 11.4.3 ITRS scaling of power noise.- 11.5 Implications of noise scaling.- 11.6 Summary.- 12. Impedance Characteristics of Multi-Layer Grids.- 12.1 Electrical properties of multi-layer grids.- 12.1.1 Impedance characteristics of individual grid layers.- 12.1.2 Impedance characteristics of multi-layer grids.- 12.2 Case study of a two layer grid.- 12.2.1 Simulation setup.- 12.2.2 Inductive coupling between grid layers.- 12.2.3 Inductive characteristics of a two layer grid.- 12.2.4 Resistive characteristics of a two layer grid.- 12.2.5 Variation of impedance with frequency in a two layer grid.- 12.3 Design implications.- 12.4 Summary.- 13. Inductive Effects In On-Chip Power Distribution Networks.- 13.1 Scaling effects in chip-package resonance.- 13.2 Propagation of power distribution noise.- 13.3 Local inductive behavior.- 13.4 Summary.- 14. Conclusions.- References.- About the Authors.

Power Distribution Networks in High Speed Integrated Circuits

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered.

/pdf/inductive-properties-of-high-performance-power-distribution-3dvv6hwgs7.pdf

Inductive properties of high-performance power distribution grids

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks

Andrey V. Mezhiba

Papers

Power Distribution Networks with On-Chip Decoupling Capacitors

Scaling trends of on-chip power distribution noise

Power Distribution Networks in High Speed Integrated Circuits

Inductive properties of high-performance power distribution grids

On-Chip Power Delivery and Management