Large-scale (or massive) multiple-input multiple-out put (MIMO) is expected to be one of the key technologies in next-generation multi-user cellular systems based on the upcoming 3GPP LTE Release 12 standard, for example. In this work, we propose-to the best of our knowledge-the first VLSI design enabling high-throughput data detection in single-carrier frequency-division multiple access (SC-FDMA)-based large-scale MIMO systems. We propose a new approximate matrix inversion algorithm relying on a Neumann series expansion, which substantially reduces the complexity of linear data detection. We analyze the associated error, and we compare its performance and complexity to those of an exact linear detector. We present corresponding VLSI architectures, which perform exact and approximate soft-output detection for large-scale MIMO systems with various antenna/user configurations. Reference implementation results for a Xilinx Virtex-7 XC7VX980T FPGA show that our designs are able to achieve more than 600 Mb/s for a 128 antenna, 8 user 3GPP LTE-based large-scale MIMO system. We finally provide a performance/complexity trade-off comparison using the presented FPGA designs, which reveals that the detector circuit of choice is determined by the ratio between BS antennas and users, as well as the desired error-rate performance.

Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations

EURASIP Journal on Applied Signal Processing

In the areas of signal processing and communications, such as antenna-array beamforming, adaptive filtering, multiuser and multiple-input-multiple-output (MIMO) detection, channel estimation and equalization, echo and interference cancellation, and others, solving linear systems of equations often provides an optimal performance. However, this is also a very complicated operation that designers try to avoid by proposing different suboptimal techniques. The dichotomous coordinate descent (DCD) algorithm allows linear systems of equations to be solved with high computational efficiency. In this paper, we present architectures and field-programmable gate-array (FPGA) designs of two variants of the DCD algorithm, which are known as cyclic and leading DCD algorithms. For each of these techniques, we present serial designs, group-2 and group-4 designs, as well as a design with parallel update of the residual vector for the cyclic DCD algorithm. These designs have different degrees of parallelism, thus enabling a tradeoff between FPGA resources and computation time. The serial designs require the smallest FPGA resources; they are well suited for applications where many parallel solvers are required, e.g., for detection in MIMO-orthogonal-frequency-division-multiplexing communication systems. The parallelism introduced in the proposed group-2 and group-4 designs allows faster convergence to the true solution at the expense of an increase in FPGA resources. The design with parallel update of the residual vector provides the fastest convergence speed; however, if the system size is high, it may result in a significant increase in FPGA resources. The proposed fixed-point designs provide an accuracy performance that is very close to the performance of floating-point counterparts and require significantly lower FPGA resources than techniques based on QR decomposition.

Architecture and FPGA Design of Dichotomous Coordinate Descent Algorithms

Real-time matrix inversion is a key enabling technology in multiple-input multiple-output (MIMO) communications systems, such as 802.11n. To date, however, no matrix inversion implementation has been devised which supports real-time operation for these standards. In this paper, we overcome this barrier by presenting a novel matrix inversion algorithm which is ideally suited to high performance floating-point implementation. We show how the resulting architecture offers fundamentally higher performance than currently published matrix inversion approaches and we use it to create the first reported architecture capable of supporting real-time 802.11n operation. Specifically, we present a matrix inversion approach based on modified squared Givens rotations (MSGR). This is a new QR decomposition algorithm which overcomes critical limitations in other QR algorithms that prohibits their application to MIMO systems. In addition, we present a novel modification that further reduces the complexity of MSGR by almost 20%. This enables real-time implementation with negligible reduction in the accuracy of the inversion operation, or the BER of a MIMO receiver based on this.

QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers

Devices and methods are provided for directionally receiving and/or transmitting acoustic waves and/or radio waves for use in applications such as wireless communications systems and/or radar. High directional gain and spatial selectivity are achieved while employing an array of receiving antennas that is small as measured in units of the wavelength of radio waves being received or transmitted, especially in the case of spatially oversampled arrays. Frequency/wavenumber, multi-dimensional spectrum analysis, as well as one-dimensional frequency spectrum analysis can be performed.

Beamforming devices and methods

Design and implementation of a highly optimized MIMO (multiple-input multiple-output) detector requires cooptimization of the algorithm with the underlying hardware architecture. Special attention must be paid to application requirements such as throughput, latency, and resource constraints. In this work, we focus on a highly optimized matrix inversion free 4 × 4 MMSE (minimum mean square error) MIMO detector implementation. The work has resulted in a real-time field-programmable gate array-based implementation (FPGA-) on a Xilinx Virtex-2 6000 using only 9003 logic slices, 66 multipliers, and 24 Block RAMs (less than 33% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput with a small 2.77-microsecond latency. The designed 4 × 4 linear MMSE MIMO detector is capable of complying with the proposed IEEE 802.11n standard.

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A practical, hardware friendly MMSE detector for MIMO-OFDM-based systems

Certain disclosed embodiments pertain to suppressing interference in a wireless communication system For example, a method of suppressing interference can include receiving one or more first signals including components from a plurality of sub-channels Each of the first signals can be converted into a respective plurality of first sub-band frequency components A respective spatial filter can be determined for each frequency sub-band using one or more corresponding first sub-band components for each respective spatial filter One or more second signals including components from the plurality of sub-channels can be received Each of the second signals can be converted into a respective plurality of second sub-band frequency components A corresponding plurality of filtered sub-band components can be generated by applying the respective spatial filters to the corresponding second sub-band components for each of the second signals

Wideband interference mitigation for devices with multiple receivers

Methods and systems for mitigating interference or estimating a covariance matrix in a communication system are disclosed. In some embodiments, a method of demodulating a received signal in a communication system includes receiving a first plurality of waveforms, estimating a covariance matrix based on the first plurality of waveforms, determining a spatial filter based on the estimated covariance matrix, receiving a second plurality of waveforms, generating at least one filtered waveform by applying the spatial filter to the second plurality of waveforms, and demodulating the at least one filtered waveform.

Interference mitigation for devices with multiple receivers

This paper reports on a highly optimized 4×4 MMSE detector implementation. The work resulted in a real-time FPGA based implementation on a Xilinx Virtex-II 6000 part. It utilizes 8,513 logic slices, 64 multipliers, and 23 Block RAMs (less than 30% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput, with a small 2.77 μs latency. Three main techniques are responsible for the improvements over other MIMO detectors reported in literature. They are: (a) the combination of a modified Gram-Schmidt QR decomposition algorithm with Square-Root linear MMSE detection; (b) a dynamic scaling algorithm that enhances numerical stability; and (c) an aggressive time-shared VLSI architecture. The above techniques are quite general and are readily applicable to any MIMO detector implementation.

An efficient FPGA based MIMO-MMSE detector

A real time, 2 Mbps to 200 Mbps portable radio unit with MIMO and sensing capability which exposes all the PHY parameters to the higher layers will help advance experimental cognitive radio (CR), and wireless networking research. Collaboration between Silvus Communication Systems and the UCLA WISR group has resulted in the first generation radio specifically designed to meet the needs of the CR and wireless networking community. The current platform is based on a COTS FPGA platform with dual-band RF capabilities. It implements a slight variant of the 802.11n draft spec. It is a fully self contained PHY solution with over 100 unique modes of operation. Moreover it features a robust API to the MAC through which all PHY parameters can be controlled on a per-packet basis. The same API will allow the PHY to communicate channel state information, SNR, and RSSI measurements to the MAC. A 16 micro-second packet decode latency ensures that the PHY processing does not inhibit the system's fast response to changing channel and interference condition.

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Anish Shah

Papers

A practical, hardware friendly MMSE detector for MIMO-OFDM-based systems

Wideband interference mitigation for devices with multiple receivers

Interference mitigation for devices with multiple receivers

An efficient FPGA based MIMO-MMSE detector

A real time MIMO OFDM testbed for cognitive radio & networking research