Open AccessProceedings Article
An efficient FPGA based MIMO-MMSE detector
Hun-Seok Kim,Weijun Zhu,Jatin Bhatia,Karim Mohammed,Anish Shah,Babak Daneshrad +5 more
- pp 1131-1135
TLDR
This paper reports on a highly optimized 4×4 MMSE detector implementation that resulted in a real-time FPGA based implementation on a Xilinx Virtex-II 6000 part that delivers over 420 Mbps sustained throughput, with a small 2.77 μs latency.Abstract:
This paper reports on a highly optimized 4×4 MMSE detector implementation. The work resulted in a real-time FPGA based implementation on a Xilinx Virtex-II 6000 part. It utilizes 8,513 logic slices, 64 multipliers, and 23 Block RAMs (less than 30% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput, with a small 2.77 μs latency. Three main techniques are responsible for the improvements over other MIMO detectors reported in literature. They are: (a) the combination of a modified Gram-Schmidt QR decomposition algorithm with Square-Root linear MMSE detection; (b) a dynamic scaling algorithm that enhances numerical stability; and (c) an aggressive time-shared VLSI architecture. The above techniques are quite general and are readily applicable to any MIMO detector implementation.read more
Citations
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Journal ArticleDOI
Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations
TL;DR: This work proposes a new approximate matrix inversion algorithm relying on a Neumann series expansion, which substantially reduces the complexity of linear data detection in single-carrier frequency-division multiple access (SC-FDMA)-based large-scale MIMO systems.
Journal ArticleDOI
Architecture and FPGA Design of Dichotomous Coordinate Descent Algorithms
Jie Liu,Yuriy Zakharov,B. Weaver +2 more
TL;DR: This paper presents architectures and field-programmable gate-array designs of two variants of the DCD algorithm, known as cyclic and leading DCD algorithms, and proposes fixed-point designs that provide an accuracy performance that is very close to the performance of floating-point counterparts and require significantly lower FPGA resources than techniques based on QR decomposition.
Proceedings ArticleDOI
Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison
P. Luethi,Christoph Studer,S. Duetsch,Eugen Zgraggen,Hubert Kaeslin,Norbert Felber,Wolfgang Fichtner +6 more
TL;DR: An optimized fixed-point VLSI implementation of the modified Gram-Schmidt (MGS) QRD algorithm that incorporates regularization and additional sorting of the MIMO channel matrix that clearly showed superiority of the Givens rotation (GR) solution in terms of area, processing cycles, and throughput.
Patent
Wideband interference mitigation for devices with multiple receivers
TL;DR: In this paper, a method of suppressing interference can include receiving one or more first signals including components from a plurality of sub-channels each of the first signals can be converted into a respective plurality of first sub-band frequency components.
Patent
Interference mitigation for devices with multiple receivers
TL;DR: In this paper, a method of demodulating a received signal in a communication system includes receiving a first plurality of waveforms, estimating a covariance matrix based on the first plurality, determining a spatial filter based on estimated covariance, and generating at least one filtered waveform by applying the spatial filter to the second plurality.
References
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