Radiation-induced single event transients (SETs) are expected to evolve to single event multiple transients (SEMTs) due to the downscaling of transistor feature size, which also increases the difficulty of the vulnerability estimation for large-scale digital integrated circuits. In this paper, a novel layout-based soft error vulnerability estimation approach which is termed LBSEVEA is proposed to evaluate the impact of heavy ions on the vulnerability of combinational circuits. The physical process of interaction between particles and devices, especially nuclear reaction and scattering process are included in the LBSEVEA. In addition, ambipolar diffusion and bipolar amplification effect, which induce additional charge collection of the adjacent transistors and the hitting transistor, are also considered. A new method calculating the collected charge induced by the bipolar amplification effect is presented. By introducing the layout information of the target circuits into the identification of the adjacent cells, SEMTs effect can be considered in the vulnerability estimation. A fast SPICE simulation tool is adopted to conduct the fault injected netlist simulations, which can make a favorable compromise between the consumption of computer resources and simulation precision. Furthermore, induced soft error numbers, distributions of charge collected by the hitting nodes and the adjacent nodes, and SET pulse width distributions are presented. Besides, heatmaps of induced pulse widths for the layout of two benchmark circuits are provided. Finally, the constraints, the flexibility, and the scalability of the LBSEVEA are discussed. The ability to estimate the impact of process variations on the vulnerability is also presented. Compared with simulation and experimental results, the LBSEVEA can fairly estimate the vulnerability of combinational circuits.

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)

Single-event effects induced by medium-energy protons in 28 nm system-on-chip

Effect of temperature and single event transient on crosstalk in coupled single-walled carbon nanotube (SWCNT) bundle interconnects

The present invention discloses a fast, low-overhead and full-automatic digital integrated circuit single-particle fault injection system. The system comprises a man-machine operation interface and a fault injector; the fault injector comprises a fault circuit netlist code generation module, a function vector and fault random signal generation module and a simulation statistics and calculation output module. With the system of the invention adopted, full automatic single-particle fault injection is realized; a process files is processed in real time, so that influence on simulation performance caused by memory explosion due to excessively large storage quantity can be avoided; and the overhead of a calculator for simulation can be reduced.

Fast, low-overhead and full-automatic digital integrated circuit single-particle fault injection system

Effect of HAF carbon black on curing, mechanical, thermal and neutron shielding properties of natural rubber - Low-density polyethylene composites

The present invention provides a storage unit resistant to multi-node inversion, and relates to the technical field of integrated circuits, so as to solve a problem that incapability of an existing storage unit in a radiation environment in resisting single-particle multi-node inversion causes a storage state of the storage unit to change. The storage unit comprises: a PMOS transistor 1, a PMOS transistor 2, a PMOS transistor 3, a PMOS transistor 4, an NMOS transistor 1, an NMOS transistor 2, an NMOS transistor 3, an NMOS transistor 4, an NMOS transistor 5, an NMOS transistor 6, an NMOS transistor 7, an NMOS transistor 8, a word line WL, a bit line BL, and a bit line BLN. The storage unit provided by the present invention can resist single-particle single-node inversion and single-particle multi-node inversion, and prevent an SEU effect from changing the storage state of the storage unit, thereby improving system reliability. The storage unit is applicable to an integrated circuit.

Storage unit resistant to multi-node inversion

Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

The invention relates to an observation point and concurrence based fault injection simulation method and device, and belongs to the field of integrated circuit fault injection simulation methods In order to solve a defect that a fault injection simulation method in the prior art is too long in simulation time because of adoption of a single observation point and a single process, the invention provides an observation point and concurrence based fault injection simulation method The method comprises the steps of acquiring test data from description codes of a target circuit; setting fault injection parameters; setting a preset number of observation points in allusion to the test data, performing fault injection by adopting a concurrent mode, and generating an output file; detecting whether the target circuit operates normally or not at the next observation point after each period of fault injection, if so, performing the next period of injection, and if not, turning back to the previous observation point to start the next period of fault injection; and analyzing the output file to acquire a fault analysis result The invention further comprises an observation point and concurrence based fault injection simulation device The method and device provided by the invention can applicable to radiation resistance performance evaluation for integrated circuits

Observation point and concurrence based fault injection simulation method and device

Pore-water pressure response of a silty seabed to random wave action: Importance of low-frequency waves

This paper proposed a method to estimate cross-section of circuits at RTL level design. By combination of the intrinsic cross-section which was obtain from Monte-Carlo simulation with the results obtained from fault injection, the method can provide systematic dynamic cross-section of the design. It can be an alternative method instead of ground radiation test to get cross section. The DDC IP Core has been simulated for test. The results showed that dynamic cross-section is smaller than static cross-section in certain application. The saturated dynamic cross-section of it is about 5e-3 cm2/device.

Anlong Li

Papers

Storage unit resistant to multi-node inversion

Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

Observation point and concurrence based fault injection simulation method and device

Pore-water pressure response of a silty seabed to random wave action: Importance of low-frequency waves

A method to estimate cross-section of circuits at RTL levels