The first shift-register 1 has 4 bits×N stages for storing the operated result BCD data 4 bits by 4 bits from LSD. The second shift-register 2 has 4 bits×M stages for storing a BIN data to be translated 4 bits by 4 bits from MSD. The D-F/F 5 is to store the output from the first shift-register 1 and the intermediate result, and output thereof is supplied to the arithmetic/logic circuit 6 through the first selector 3. The output of the second shift-register 2 is selected by the second selector 4 to be supplied to the arithmetic/logic circuit 6. The arithmetic/logic circuit 6 performs×16 operation for the stored data in the shift register 1, and adding the resultant to 4 bits data stored in the shift-register 2 with carry process. The output DO of the arithmetic/logic circuit 6 is stored in the D-F/F 5 in the first half of the shift clock SCK1, and stored in the shift-register 1 in the latter half of the shift clock SCK1. The shift-register 1 makes a round, while the shift-register 2 is 1 stage shifted.

Code translation circuit for converting a binary data to a binary coded decimal data

A binary multiplier circuit wherein the product is expressed in coded form as soon as the linear (or non-coded) product is produced. When a twelve-bit binary number is multiplied by another twelve-bit binary number a twenty-four bit binary number is produced. The twenty-four bit product can be coded as an unsigned seven-bit binary number (μ-255 code) as follows. The number 33×2 11 in binary form is added to the linear product to form an augmented product. The number of leading zeroes in the augmented product is counted and the base-minus-one complement of the count is used for the three most significant bit positions of the coded product. The four next most significant bits of the augmented product, after the most significant logic 1, are used for the four least significant bit positions of the coded product. Suitable circuitry is described which allows the coding process, just described, to take place while the linear product is in the process of being formed, and produces the coded result when the final linear product is completed.

Binary multiplier circuit including coding circuit

A CPU data path portion having an ALU, an adjuster unit, a shifter unit and a shift register unit is disclosed. The CPU is capable of selectively forming the sum or difference of a first BCD operand and a second BCD operand by arithmetically combining the operands with the ALU to form binary results, the results dependent upon the arithmetic operation selected and adjusting the results with the adjuster unit into BCD, the adjustment also dependent upon the arithmetic operation selected. The CPU is further capable of selectively converting an operand from binary to BCD format or from BCD to binary format by iteratively shifting the operand between the shifter unit and the shift register unit and correcting the operand with the ALU, the direction of the shift and the ALU correction dependent upon the conversion selected.

Central processing unit having built-in BCD operation

Hollow polyester undrawn filaments having excellent mechanical quality and uniformity are prepared by a simplified post-coalescence melt spinning process at speeds of e.g. 2-5 km/min by selection of polymer and spinning conditions whereby the void content of the undrawn filaments can be essentially maintained or even increased when drawn cold or hot, with or without post heat-treatment.

Improvements in continuous hollow filaments, yarns, and tows

An arithmetic operation circuit includes: an extractor circuit that extracts one or a plurality of bits consecutive from a most significant bit or from a least significant bit of a binary number; a sum register that stores an X-adic sum, where X is an integer more than two; and an update circuit that updates the stored X-adic sum with a value obtained by adding a first X-adic number to be cyclically multiplied by a certain coefficient to the X-adic sum in accordance with the extracted one or plurality of bits.

Arithmetic operation circuit and method of converting binary number

A binary coded input signal is converted to a binary coded decimal signal having N decades by employing N four bit shift registers. The bits of the input signal are sequentially supplied, in order, to the least significant position of the register for the units decade, with the most significant bit of the input signal being applied to the units register first. Each of the registers includes a right shift-parallel load mode control input terminal. In response to the sum of the values stored in each register and the binary value 0011 being less than the binary value 1000, the mode control input terminal is activated to shift the register contents one bit to the right. In response to the sum being greater than 1000, the mode control input terminal is activated to load the sum into the register. A binary one is loaded into the least significant bit position of the register for the adjacent higher decade in response to the sum being greater than 1000.

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Anthony J. Miller

Papers

Binary to binary coded decimal converter