Patent
Binary to binary coded decimal converter
TLDR
In this article, a binary coded input signal is converted to binary coded decimal signal having N decades by employing N four-bit shift registers with a right shift-parallel load mode control input terminal.Abstract:
A binary coded input signal is converted to a binary coded decimal signal having N decades by employing N four bit shift registers. The bits of the input signal are sequentially supplied, in order, to the least significant position of the register for the units decade, with the most significant bit of the input signal being applied to the units register first. Each of the registers includes a right shift-parallel load mode control input terminal. In response to the sum of the values stored in each register and the binary value 0011 being less than the binary value 1000, the mode control input terminal is activated to shift the register contents one bit to the right. In response to the sum being greater than 1000, the mode control input terminal is activated to load the sum into the register. A binary one is loaded into the least significant bit position of the register for the adjacent higher decade in response to the sum being greater than 1000.read more
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Patent
Code translation circuit for converting a binary data to a binary coded decimal data
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References
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Patent
Serial binary coded decimal converter
TL;DR: In this article, the authors describe a converter in which the number to be converted is inserted into a shift register and the number is recirculated through the shift register in the direction of decreasing significance of the number.
Patent
Radix converter utilizing automata
TL;DR: A radix converter comprises a plurality of automata each of combined Moore and Mealy design as mentioned in this paper, connected in cascade with the digits of the input number applied serially to one of the automata.
Patent
Improvements relating to code converters
TL;DR: In this article, a system for converting a pure binary number into a binary-coded-decimal number is described, in which the pure binary numbers are shifted, most significant bit first, from a register 2 into an accumulating register 1 which is notionally divided into decimal stages R0, R10, R100, each comprising six bits, and after each shift the binary filler number 110110 ( = 2 6 - 10 = 54) is added to each decimal stage R 0, R 10..., &c., and is immediately subtracted from all those