Anthony Saporito

TL;DR: In this paper, a counter is maintained that provides a count of how often a transaction has been aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions.

TL;DR: In this article, a method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided, which includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB).

TL;DR: In this article, a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor is described, where the cache is dynamically allocated for use among the multiple threads.

TL;DR: In this article, a multiprocessor system for detecting and recovering from errors is described, where the first processor detects an error and initiates a recovery process, and the second processor synchronizes at least one recovery action during the recovery process.

TL;DR: In this article, a register file collects a history of the error state information for each core, which can be analyzed to understand the recovery sequence of events, which is useful to understand complex error scenarios.