In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we explore methods of reducing energy consumption that do not lead to performance loss (i.e. wasted energy), and explore methods to reduce delay by exploiting instruction level parallelism. We found that careful design reduced the energy dissipation by almost 25%. Pipelining can give approximately a 2/spl times/ improvement in energy-delay product. Superscalar issue, however, does not improve the energy-delay product any further since the overhead required offsets the gains in performance. Further improvements will be hard to come by since a large fraction of the energy (50-80%) is dissipated in the clock network and the on-chip memories. Thus, the efficiency of processors will depend more on the technology being used and the algorithm chosen by the programmer than the micro-architecture.

Energy dissipation in general purpose microprocessors

The power consumed within an integrated circuit (IC) is reduced without substantial impact on its performance for typical applications by throttling the performance of particular functional units within the IC. Artificial worst-case power consumption is reduced by throttling down the activity levels of long-duration sequences of high-power operations. The recent utilization levels of particular functional units within an IC are monitored--for example, by computing each functional unit's average duty cycle over its recent operating history. If this activity level is greater than a threshold, then the functional unit is operated in a reduced-power mode. The threshold value is set large enough to allow short bursts of high utilization to occur without impacting performance. The invention allows an integrated circuit to dynamically make the tradeoff between high-speed operation and low-power operation, by throttling back performance of localized functional units when their utilization exceeds a sustainable level. Additionally, this dynamic power/speed tradeoff can be optimized across multiple functional units within an IC or among multiple ICs within a system. Additionally, this dynamic power/speed tradeoff can be altered by providing software control over throttling parameters.

Performance throttling to reduce IC power consumption

A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field The microprocessor also includes a latency control register which assures that the functional unit is operational after the functional unit is placed from a low power state to a more fully operational state by changing the corresponding field in the power control register

Microprocessor having software controllable power consumption

Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device.

Thermal and power management for computer systems

Described is a data communication protocol, in which a client and server negotiate in a manner that does not require the client to retry negotiation when servers are not capable of the client-desired protocol. In one example implementation, the desired protocol is SMB 2.0 or greater. The protocol describes a create command with possibly additional context data attached for built-in extensibility, and a compound command comprising a plurality of related commands or unrelated commands. A multi-channel command requests data transfer on a separate data channel, a signed capability verification may be used to ensure that a secure connection is established, and the protocol provides the ability to transfer extended error data from the server in response to a request.

Data communication protocol

A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.

Circuitry and method for reducing power consumption within an electronic circuit

Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical address is stored in a data structure table for each page. Each virtual address includes a page virtual address which identifies the translation entry containing the physical address of the page containing the memory location. The virtual address may be translated to a translation entry index using the size of the page containing the memory location.

Method, system, and program for addressing pages of memory by an I/O device

Provided are a method, system, and program for managing data transmission from a source to a destination through a network. The destination imposes a window value on the source which limits the quantity of data packets which can be sent from the source to the destination without receiving an acknowledgment of being received by the destination. In one embodiment, the source imposes a second window value, smaller than the destination window value, which limits even further the quantity of data packets which can be sent from the source to the destination without receiving an acknowledgment of being received by the destination. In another embodiment, a plurality of direct memory access connections are established between the source and a plurality of specified memory locations of a plurality of destinations. The source imposes a plurality of message limits, each message limit imposing a separate limit for each direct memory access connection on the quantity of messages sent from the source to the specified memory location of the direct memory access connection associated with the message limit and lacking a message acknowledgment of being received by the destination of the direct memory access connection associated with the message limit.

Method, system, and program for managing data transmission through a network

Provided are a method, system, and program for updating a cache in which, in one aspect of the description provided herein, changes to data structure entries in the cache are selectively written back to the source data structure table maintained in the host memory. In one embodiment, translation and protection table (TPT) contents of an identified cache entry are written to a source TPT in host memory as a function of an identified state transition of the cache entry in connection with a memory operation and the memory operation. Other embodiments are described and claimed.

Method, system, and program for updating a cached data structure table

Provided are a method, system, and program for caching a virtualized data structure table. In one embodiment, an input/output (I/O) device has a cache subsystem for a data structure table which has been virtualized. As a consequence, the data structure table cache may be addressed using a virtual address or index. For example, a network adapter may maintain an address translation and protection table (TPT) which has virtually contiguous data structures but not necessarily physically contiguous data structures in system memory. TPT entries may be stored in a cache and addressed using a virtual address or index. Mapping tables may be stored in the cache as well and addressed using a virtual address or index.

Arturo L. Arizpe

Papers

Circuitry and method for reducing power consumption within an electronic circuit

Method, system, and program for addressing pages of memory by an I/O device

Method, system, and program for managing data transmission through a network

Method, system, and program for updating a cached data structure table

Method, system, and program for accessesing a virtualized data structure table in cache