A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

Digital phase alignment and integrated multichannel transceiver employing same

A frame synchronization method and apparatus wherein each computer system of a multiply redundant processing system periodically executes a frame synchronization procedure in which it sequentially assumes a plurality of different operating states during which it pauses in the execution of a task it was performing and readies itself for synchronization, determines which other computer systems are ready for synchronization, synchronizes itself with one or more of the systems, and then determines which of the other systems has also synchronized itself At a predetermined frame interval, the procedure is repeated and the computer systems resynchronize themselves with one another The invention is impervious to stuck-at type faults, and may be embodied either totally or partially in software within each computer system, or in a separate hardware device

Frame synchronization of multiply redundant computers

A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

Digital clock buffer circuit providing controllable delay

A system for providing fault-tolerant synchronized operation of the Time of Day (TOD) clocks of the respective data processors in a multiprocessor complex. Basically, the system is comprised of a duplex implementation having redundant TOD clock sources, and a plurality of TOD slaves which provide the TOD clocks in the associated processors. A register/counter in each TOD clock source is incremented by a high frequency signal to achieve the required TOD value resolution, and the latter signal is divided down to provide a lower reference frequency signal for synchronization of the clock sources. Each TOD slave includes means for receiving a pair of reference frequency signals and for trouble-free switching between the signals, as required. Alternately, a quad implementation of clock sources which is substantially free of single points of failure of the synchronization mechanism is described. Frequency steering of the clock sources provides increased accuracy and conformity to real time when desired.

Synchronized fault tolerant clocks for multiprocessor systems

A heartbeat collision avoidance method and system regulates the access of two or more computers to the data communications path of the local area network by allocating unique transmission slot times to each of the computers on the network in reference to the heartbeat signal which is generated independently of a data transmission. The transmission slot time of each station of the network is determined by initiating a timeout counter circuit which is triggered by the heartbeat signal and which times out at differing times in accordance with a unique address assigned to each of the network stations. The station is permitted to commence a transmission at its slot time provided the time interval between the slot time and the end of the last data transmission exceeds a predetermined interframe spacing interval. In one aspect of the invention the heartbeat signal which triggers the timeout counter circuits associated with each station is generated by a network master station which has the highest station address.

Heartbeat collision avoidance method and circuit

A clock synchronization system for use in a digital switching system including multiple clock circuits. This circuit includes multiple synchronization circuits connected in a master-slave arrangement. Each synchronization circuit includes a counter chain which provides a periodic system framing pulse and a trigger circuit which insures that its slave system framing pulse is in synchronization with the master system framing pulse.

Ashfaq R. Khan

Papers

Clock synchronization system