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Patent

Clock synchronization system

Ashfaq R. Khan, +1 more
TLDR
A clock synchronization system for use in a digital switching system including multiple clock circuits is described in this paper, where a clock synchronization circuit includes a counter chain which provides a periodic system framing pulse and a trigger circuit which insures that its slave system framer is in synchronization with the master system.
Abstract: 
A clock synchronization system for use in a digital switching system including multiple clock circuits. This circuit includes multiple synchronization circuits connected in a master-slave arrangement. Each synchronization circuit includes a counter chain which provides a periodic system framing pulse and a trigger circuit which insures that its slave system framing pulse is in synchronization with the master system framing pulse.

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Citations
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Patent

Digital phase alignment and integrated multichannel transceiver employing same

Christos John Georgiou, +2 more
TL;DR: In this paper, a synchronizer and phase aligning method that provides signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc.
Patent

Frame synchronization of multiply redundant computers

Vijay C. Jaswa
TL;DR: In this article, a frame synchronization method and apparatus for multiply redundant processing systems is proposed, which is impervious to stuck-at type faults, and may be embodied either totally or partially in software within each computer system, or in a separate hardware device.
Patent

Digital clock buffer circuit providing controllable delay

W. Daniel Hillis, +4 more
TL;DR: In this paper, a clock buffer circuit that generates a local clock signal in response to a system clock signal was proposed, where the buffer control circuit provides a variable delay so that the local clock signals have a selected phase relationship in relation to the system clock signals.
Patent

Synchronized fault tolerant clocks for multiprocessor systems

Thomas Basil Smith
TL;DR: In this article, a fault-tolerant synchronized operation of the Time of Day (TOD) clocks of the respective data processors in a multiprocessor complex is described.
Patent

Heartbeat collision avoidance method and circuit

Michael Barall
TL;DR: In this paper, the authors propose a heartbeat collision avoidance method and system regulates the access of two or more computers to the data communications path of the local area network by allocating unique transmission slot times to each of the computers on the network in reference to the heartbeat signal which is generated independently of a data transmission.
References
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Patent

Redundant clock signal generating circuitry

Deborah L. Moreau
TL;DR: In this paper, a clock signal generator for providing redundant clock signals includes two clock modules that utilize phase-locked loop oscillators for generating clock and reference signals and for diagnosing malfunctions of the generated clock and references signals.
Patent

High reliability active-standby clock arrangement

Ernest Gomez
TL;DR: In this paper, a clock pulse circuit is described in which two clock pulse generators operate in an active-standby circuit arrangement to provide a highly reliable single clock output signal comprising a sequence of repetitive pulses.
Patent

Standby apparatus for clock signal generators

Joseph Michael Fallon, +1 more
TL;DR: In this article, a clock output signal is aligned in phase to conicide with the phase of signals derived from a master clock in the event of a malfunction of the master clock.