From the dawn of the VLSI based approach for the digital signal processing at most research is centered upon the digital filters and their designing, as filters are the circuit elements which are mainly used in signal processing where among these digital filters the group of filters that have finite duration of impulse response are called FIR(finite impulse response) filters and are having the preference over other groups of filters in the classification as their linearity and standard signal processing characteristics are conducive for implementing in microprocessors and DSP’s(digital signal processor). As the ever-changing reforms in technology take place, a system with reconfigurable design has to be provided in order to cope up with the transitions in the research timeline and since there have been many years of ongoing research in the branch of FIR filters with reconfigurable design an analysis of this research is presented by studying the design approach and proposed architectures by various researchers from the last 20 years.

Reconfigurable FIR Filters: A survey

A parasitic insensitive passive switched‐capacitor interpolation finite impulse response filter

AbstractIn this paper, a review on some of the techniques of designing the FIR filter efficiently has been presented. Most of the Digital Signal Processing (DSP) devices use digital FIR filter due to its various advantages over IIR filter. In designing these filters, there are many performance parameters like area, power consumption, speed and complexity, which put challenges in front of a designer. In order to meet the desired performance, many techniques have been proposed. This paper is mainly focused on some of these techniques.KeywordsAdaptive filterDigital Signal Processing (DSP)Distributed Arithmetic (DA)FIR filterReconfigurable 

Efficient Techniques for FIR Filter Designing

Power consumption is the most crucial point of designing any architecture. Till the date so many techniques have been discussed for realizing Digital filters more power efficient. This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm. As multiplier takes the maximum area of any hardware and consumes the highest power so here in this design it is optimized using realizing the multiplier with the help of adder and shifter. FIR filter is symmetrical and has linear phase so stable and easy to implement and supports the number of DSP system. Power analysis shows that the above architecture consumes less power than the traditional one.

Asmita Wachaspati

Papers

A custom reconfigurable power efficient FIR filter