Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Electronic devices and systems, and methods for making and using the same

At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.

Method of Manufacturing a Semiconductor Device

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

Integrated circuit package including miniature antenna

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

Clock data recovery circuitry associated with programmable logic device circuitry

An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC. In some embodiments, an interface cell has a pad that is usable for receiving a digital signal or for receiving an analog signal. The interface cell includes special dedicated analog circuitry that has a differential input lead that is programmably couplable to the pad.

Realizing analog-to-digital converter on a digital programmable integrated circuit

An FPGA has an on-chip processor that reads configuration data onto the FPGA and controls the loading of that configuration data into FPGA configuration memory cells. After FPGA power-up, the processor reads a configuration mode code from predetermined terminals of the FPGA. If the configuration mode code has a first value, then the processor executes a first configuration program so that configuration data is received onto the FPGA in accordance with a first configuration mode. If the configuration mode code has a second value, then the processor executes a second configuration program so that configuration data is received onto the FPGA in accordance with a second configuration mode. The configuration programs can be stored in metal-mask ROM on-chip so they can be changed without re-laying out the remainder of the FPGA. Providing multiple configuration programs allows the FPGA to support multiple configuration modes using the same processor hardware. One configuration mode code causes the processor to execute a loader program that in turn loads a configuration program onto the FPGA from a source external to the FPGA. Once the configuration program is loaded, the processor executes the configuration program thereby allowing the FPGA to support a custom configuration mode.

Supporting multiple FPGA configuration modes using dedicated on-chip processor

A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory stores of a plurality of check words. A buffer circuit is coupled to the check memory and to the frame circuit. The buffer circuit assembles blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory. A plurality of storage elements are provided for storage of status information. A check circuit is coupled to the storage elements and to the buffer circuit. Each block is checked by the check circuit using an error correcting code, and data indicating detected errors is stored in the storage elements.

FPGA configuration memory with built-in error correction mechanism

A field programmable gate array (FPGA) device includes a high-speed serializer/deserializer (SERDES). The field programmable gate array allows programmable built-in testing of the SERDES at operating speeds. A digital clock manager circuit allows clock signals coupled to the SERDES to be modified during the test operations to stress the SERDES circuit. The logic array of the FPGA can be programmed to generate test patterns and to analyze data received by the SERDES circuit. Cyclic redundancy check (CRC) characters, or other error checking characters, can also be generated using the logic array. During testing, the FPGA can perform extensive tests on the communication circuitry and store the results of the testing. An external tester can read the results of the test without substantial test time or complicated test equipment. After testing is complete, the device may be re-programmed to perform the end-user function, adding zero cost to the device for test implementation.

Integrated testing of serializer/deserializer in fpga

A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step. The programmable loop filter is controlled to realize the selected loop filter and the selected loop filter is switched into a control loop involving the second phase detector. The control loop controls the oscillator to achieve phase lock by varying a supply voltage supplied to the oscillator.

Austin H. Lesea

Papers

Realizing analog-to-digital converter on a digital programmable integrated circuit

Supporting multiple FPGA configuration modes using dedicated on-chip processor

FPGA configuration memory with built-in error correction mechanism

Integrated testing of serializer/deserializer in fpga

Phase-locked loop employing programmable tapped-delay-line oscillator