The present invention describes a system and method for communicating voice and data over a packet-switched network that is adapted to coexist and communicate with a legacy PSTN. The system permits packet switching of voice calls and data calls through a data network from and to any of a LEC, a customer facility or a direct IP connection on the data network. The system includes soft switch sites, gateway sites, a data network, a provisioning component, a network event component and a network management component. The system interfaces with customer facilities (e.g., a PBX), carrier facilities (e.g., a LEC) and legacy signaling networks (e.g., SS7) to handle calls between any combination of on-network and off-network callers. The soft switch sites provide the core call processing for the voice network architecture. The soft switch sites manage the gateway sites in a preferred embodiment, using a protocol such as the Internet Protocol Device Control (IPDC) protocol to request the set-up and tear-down of calls. The gateway sites originate and terminate calls between calling parties and called parties through the data network. The gateway sites include network access devices to provide access to network resources. The data network connects one or more of the soft switch sites to one or more of the gateway sites. The provisioning and network event component collects call events recorded at the soft switch sites. The network management component includes a network operations center (NOC) for centralized network management.

Voice over data telecommunications network architecture

A telecommunications switching system employing multi-protocol routing optimization which utilizes predetermined and measured parameters in accordance with a set of user priorities in determining the selection of a telecommunications path to be utilized for transmitting a data file to a remote destination. The switching system has a first memory for storing the data file to be transferred, a second memory for storing predetermined parameters such as cost data associated with each of the telecommunications paths, a third memory for storing a set of user priorities regarding the transmission of data files, and means for measuring the value of variable parameters such as file transfer speed associated with each of the telecommunications paths. Processor means are operatively associated with the second and third memories and the variable parameter measuring means for determining which of the plurality of telecommunications paths should be utilized for transferring the data file in accordance with the set of user priorities, the predetermined telecommunications path parameters, and the measured variable parameters. The switching system further comprises input means for allowing a user to change the user priorities in the third memory prior to transmitting a file.

Multi-protocol telecommunications routing optimization

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.

Multiprocessor node controller circuit and method

A modular, expandable, non-blocking system for cross-connecting high speed digital signals is provided. The system is capable of connecting DSn, CEPTn, and STSn signals as desired, with lower rate signals being included as components of the high-rate signals or terminating on low speed lines, as desired. The system accomplishes its goals by converting all incoming signals into a substantially SONET format, and by processing all the signals in that format. The signals are typically cross-connected in the substantially SONET format, although an expandable non-blocking wide band cross-connect module is provided which cross-connects any like signals. If the outgoing signal is to be in other than SONET format, the substantially SONET formatted signal is reconverted into its outgoing format. To create a complete system, various modules are utilized, including: add/drop multiplexer means for add/drop applications of DS-0, DS-1, CEPTn signals, etc.; a SONET bus interface; a virtual tributary cross-connect module which cross-connects virtual tributary payloads in space, time, and phase to generate new substantially SONET formatted signals; a wide band cross-connect module; a DS-3/SONET converter; and front end interfaces including a DS3 line interface, and various STSn interfaces. The modules may be mixed and matched as desired to accommodate a multitude of applications.

System for cross-connecting high speed digital signals

In a multicomputer, concurrent computing system having a plurality of computing nodes, this is a method and apparatus for routing message packets between the nodes. The method comprises providing a routing circuit at each node and interconnecting the routing circuits to define communications paths interconnecting the nodes along which message packets can be routed; at each routing circuit, forming routes to other nodes as a sequence of direction changing and relative address indicators for each node between the starting node and each destination node; receiving a message packet to be transmitted to another node and an associated destination node designator therefor; retrieving the route to the destination node from a memory map; adding the route to the destination node to the beginning of the message packet as part of a header; transmitting the message packet to the routing circuit of the next adjacent node on the route to the destination node; and at each intermediate node, receiving the message packet; reading the header; directing the message packet to one of two outputs thereof as a function of routing directions in the header, updating the header to reflect passage through the routing circuit; and at the destination node, stripping remaining portions of the header from the message packet; storing the message packet; and, informing the node that the message packet has arrived.

Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network

A communication method and packet switching network (101) in which self-routing packets are communicated via multipaths through the network while maintaining the sequence of the packets. The switching network has a plurality of stages (0, 1, 2, 3) the stages are interconnected by inter-node links (204, 205, 206). Each inter-node link comprises a pair of sublinks (204-0, 204-1, 205-0, 205-1) thus establishing multipaths through the switching network in response to the self-routing packets. Each stage has a plurality of switch nodes. A switch node is responsive to packets received on one inter-node link destined for a second inter-node link to maintain the sequence of packets as they are communicated out on the second inter-node link. Each node comprises a plurality of input circuits (700-703) each individually connected to one of the incoming sublinks and a plurality of output circuits (736, 737) each connected to one of the outgoing inter-node links. Each output circuit has an arbiter (734, 735) which properly sequences the packets onto the outgoing link in response to requests for communicating packets received from the input circuits.

A self-routing multipath packet switching network with sequential delivery of packets.

A communication method and packet switching network (101) in which self-routing packets are communicated among stages of switching nodes via inter-stage links (204-215) whereon data of the packets is transmitted in one direction (210) and the packet clocking signals are transmitted in the other direction (211). Upon having the capability to accept a packet from one of the interstage links, a switch node transmits the packet clock signals to the upstream stage connect to that link indicating the present capacity to accept a packet. Furthermore, each switch node after receiving the end of a packet from an upstream stage waits for a predefined duration of time before commencing the transmission of the packet clocking signals. That delay allows the transmitting switch node i the upstream stage to determine that the link and downstream node are functioning correctly since continued transmission of the packet clock signals indicates that the packet had not been received or that downstream node had incorrectly responded to receipt of the packet. If a malfunction is detected, an error indication is transmitted to the computer controlling the switching network.

Reliable synchronous inter-node communication in a self-routing network

A switch node for the communication of circuit switched and packet information via parallel electrical and photonic connections within the node between input links and output links. The links each have electrical and optical sublinks. A node is responsive to an address received via the electrical sublink of an input link to establish both an electrical and photonic connection for the subsequent communication of both electrical and photonic data to an output link designated by the address. The switch node selects the designated output link from a set of similarly address designated output links all of which are equally capable of establishing the path. Based on this type of selection within the node, a switching network with a plurality of stages using the nodes has multipaths between any given input port to any output port.

A self-routing switch node combining electronic and photonic switching

A self-routing packet switching network (100) in which packets are communicated through stages of the network in response to self-contained addresses (Fig. 2) and in which a packet is discarded if a packet cannot be transferred to a subsequent stage of the network within a predefined amount of time. In addition, upon a packet being discarded, a maintenance message is transmitted over a maintenance channel (140) to the processor (149) controlling the network. Each network comprises stages of switching nodes which are responsive to the physical address in a packet to communicate the packet to a designated subsequent node (100-15). The nodes provide for variable packet buffering, packet address rotation techniques, and inter-node and intra-node signaling protocols. Each node comprises a timer (531) which commences timing for a predefined amount of time upon receipt of a packet. If the timer times out, the packet is discarded and a maintenance message is transmitted to the processor controlling the network. The maintenance message includes the physical address plus an address identifying the network entry point of the packet. By discarding packets after a predefined amount of time, the problem of a self-routing network locking up is avoided when one switching node within the network fails or is experiencing overload traffic conditions.

Lockup detection and recovery in a packet switching network

A packet switching arrangement in which packet retransmission is provided by the network for packets found by the network to be unusable. A packet switch node is equipped with a packet path and a control signaling path cooperating with packet address route arbitration and gating circuitry for effecting the packet retransmission. As a packet from a network input unit is passed from switch node to switch node a control signaling path through the switch nodes back to the input unit originating the packet is established. When a switch node detects an unusable packet a retransmit control signal is returned via the control signaling path to the input unit originating the packet. The input unit responds to the retransmit signal by resending the original packet. An unusable packet is blocked from further transmission in one embodiment and marked for removal at the network output ports in another embodiment. Unusable packets result from packet corruption or from packet collision within a switch node.

Avinash Kashinath Vaidya

Papers

A self-routing multipath packet switching network with sequential delivery of packets.

Reliable synchronous inter-node communication in a self-routing network

A self-routing switch node combining electronic and photonic switching

Lockup detection and recovery in a packet switching network

Packet switching arrangement including packet retransmission