Beyond energy, the growing number of defects in physical substrates is becoming another major constraint that affects the design of computing devices and systems. As the underlying semiconductor technologies are getting less and less reliable, the probability that some components of computing devices fail also increases, preventing designers from realizing the full potential benefits of on-chip exascale integration derived from near atomic scale feature dimensions. As the quest for performance confronts permanent and transient faults, device variation, and thermal issues, major breakthroughs in computing efficiency are expected to benefit from unconventional and new models of computation, such as brain-inspired computing. The challenge is then to find not only high-performance and energy-efficient, but also fault-tolerant computing solutions. Neural computing principles remain elusive, yet as source of a promising fault-tolerant computing paradigm. In the quest to fault tolerance can be translated into scalable and reliable computing systems, hardware design itself and/or to use circuits even with faults has further motivated research on neural networks, which are potentially capable of absorbing some degrees of vulnerability based on their natural properties. This paper presents a survey on fault tolerance in neural networks manly focusing on well-established passive techniques to exploit and improve, by design, such potential but limited intrinsic property in neural models, particularly for feedforward neural networks. First, fundamental concepts and background on fault tolerance are introduced. Then, we review fault types, models, and measures used to evaluate performance and provide a taxonomy of the main techniques to enhance the intrinsic properties of some neural models, based on the principles and mechanisms that they exploit to achieve fault tolerance passively. For completeness, we briefly review some representative works on active fault tolerance in neural networks. We present some key challenges that remain to be overcome and conclude with an outlook for this field.

Fault and Error Tolerance in Neural Networks: A Review

Do you need to know what technique to use to evaluate the reliability of an engineered system? This self-contained guide provides comprehensive coverage of all the analytical and modeling techniques currently in use, from classical non-state and state space approaches, to newer and more advanced methods such as binary decision diagrams, dynamic fault trees, Bayesian belief networks, stochastic Petri nets, non-homogeneous Markov chains, semi-Markov processes, and phase type expansions. Readers will quickly understand the relative pros and cons of each technique, as well as how to combine different models together to address complex, real-world modeling scenarios. Numerous examples, case studies and problems provided throughout help readers put knowledge into practice, and a solutions manual and Powerpoint slides for instructors accompany the book online. This is the ideal self-study guide for students, researchers and practitioners in engineering and computer science.

Reliability and Availability Engineering: Modeling, Analysis, and Applications

This paper presents a brief history of fault-tolerant computing. This is followed by a survey of architectural approaches to fault-tolerant design, emphasizing the basic concepts employed in the design of these systems, and the tradeoffs and alternatives available to the system designer in attempting to meet applications requirements. Classes of fault-tolerance applications are identified, along with design approaches which are applicable, and several problem areas are identified in which new research results are badly needed.

Fault-Tolerant Computing&#8212;Concepts and Examples

In order to take full advantage of VLSI, new design methods are necessary to improve the yield and testability. Designs which incorporate redundancy to improve the yields of high density memory chips are well known. The goal of this paper is to motivate the extension of this technique to other types of VLSI logic circuits. The benefits and the limitations of on-chip modularization and the use of spare elements are presented, and significant yield improvements are shown to be possible.

Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs

Experiences in Fault Tolerant Computing, 1947-1971.- Evolution of Fault Tolerant Switching Systems in AT&T.- Fault Tolerance in Tandem Computer Systems.- Evolution of Reliable Computing in Hitachi and Autonomous Decentralized System.- A History of Research in Fault Tolerant Computing at SRI International.- The Evolution of Fault Tolerant Computing at the Charles Stark Draper Laboratory, 1955-85.- The Evolution of Fault Tolerant Computing at the Jet Propulsion Laboratory and at UCLA: 1955-1986.- Dependable Computing and Fault Tolerance at LAAS: a Summary.- Reliable Digital Systems and Related Stanford University Research.- Design Fault Tolerance.- The Evolution of Fault Tolerant Computing at the University of Illinois.- The Evolution of Fault Tolerant Computing at the University of Michigan.- Experimental Research in Reliable Computing at Carnegie Mellon University.- A History of Research in Fault Tolerant Computing at the Grenoble University.- Research Activities on FTC in Japan.- The Evolution of Dependable Computing in Italy.- Fault Tolerant Computing Systems in Germany.- The Technical Committee on Fault Tolerant Computing of The IEEE Computer Society.- Biographies.- Author Index.

The evolution of fault-tolerant computing

The diversified nature of fault-tolerant computers led to the development of a multiplicity of reliability models which are seemingly unrelated to each other. As a result, it becomes difficult to develop automated tools for reliability analysis which are both general and efficient. Thus, the potential of reliability modeling as a practical and useful tool in the design process of fault-tolerant computers has not been fully realized. This paper summarizes the results of an extended effort to develop a unified approach to reliability modeling of fault-tolerant computers which strikes a good compromise between generality and practicality. The unified model developed encompasses repairable and nonrepairable systems and models, transient as well as permanent faults, and their recovery. Based on the unified model, a powerful and efficient reliability estimation program ARIES has been developed.

Avizienis

Papers

A Unified Reliability Model for Fault-Tolerant Computers