Ayose Falcón

TL;DR: In this paper, a reconfigurable functional unit and method for ANNs is described, which comprises a polymorphic decoder to generate an index using non-uniform function segmentation; a lookup table (LUT) to store parameters associated with different segments of the non-Uniform Function Segmentation, and a piecewise approximation unit to compute a final result using the parameters provided from the LUT.

TL;DR: This paper proposes several solutions to reduce the effect of branch predictor delay in the performance of SMT processors, and presents an interthread pipelined branch predictor, based on creating a pipeline of interleaved predictions from different threads.

TL;DR: A two-tier hierarchical power management methodology to exploit per-tile voltage regulators and clustered last-level caches is proposed and a novel thread migration layer is included that analyzes threads running on the tiled many-core processor for shared resource sensitivity in tandem with core, cache and frequency adaptation.

TL;DR: In this article, a fine-grained cache access mechanism is described to efficiently perform convolutions in low-power accelerators, where an execution cluster comprises a plurality of processing units, the processing units to perform convolution operations using an input data array and a kernel data array.

TL;DR: An in depth evaluation of Dynamic History Length Fitting, a technique that changes the history length of a two-level branch predictor during the execution, trying to adapt to its different phases, shows that new heuristics that minimise both opportunity cost and warm-up cost could outperform significantly current variable history length techniques.