On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

We have fabricated a single-wall carbon-nanotube (CNT)-based nonvolatile memory device using SiO2–Si3N4–SiO2 (ONO) layers as a storage node. The memory device is composed of a top gate structure with a channel width of a few nanometers and the ONO layer embedded between CNT and gate electrode. When the bias voltage between the CNT and gate electrode increases to 4 V, charges are tunneled out from CNT surfaces and captured to the traps in the ONO layers. Stored charges on the trap sites make the threshold voltage shift of 60 mV and is independent of charging time, suggesting that the ONO has traps with a quasiquantized energy state. The quantized state is related to the localized high electric field associated with CNT channel. The CNT-field-effect transistor with an ONO storage node could be used for an ultrahigh-density nonvolatile memory.

Carbon-nanotube-based nonvolatile memory with oxide–nitride–oxide film and nanoscale channel

The comparison of simulated write/erase characteristics of silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile memory with different oxides SiO 2 , Al 2 O 3 and ZrO 2 as a top dielectric was made. We demonstrate, that an application of high- k dielectrics allows to decrease the write/erase programming voltage amplitude or programming time from 1 ms to 10 μs. The ZrO 2 suppresses parasitic electron injection from polysilicon gate. Also the design of SONOS memory based on high- k dielectrics is promising for terabit scale using hot carriers injection EEPROM and DRAM memory.

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A new low voltage fast SONOS memory with high-k dielectric

Defects in silicon oxynitride gate dielectric films

Charge trapping properties of electrons and holes in ultrathin nitride-oxide-silicon (NOS) structures were quantitatively determined by variable-temperature electrostatic force microscopy (EFM). From charge retention characteristics obtained at temperatures between 250 and 370°C and assuming that the dominant charge decay mechanism is thermal emission followed by oxide tunneling, we find that there are considerable deep trap centers at the nitride-oxide interface. For electron, the interface trap energy and density were determined to be about 1.52eV and 1.46×1012cm−2, respectively. For hole, these are about 1.01eV and 1.08×1012cm−2, respectively. In addition, the capture cross section of electron can be extracted to be 4.8×10−16cm2. The qualitative and quantitative determination of charge trapping properties and possible charge decay mechanism reported in this work can be very useful for the characterization of oxide-nitride-silicon based charge storage devices.

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Charge trapping properties at silicon nitride/silicon oxide interface studied by variable-temperature electrostatic force microscopy

The chemical composition and structure of Si3N4/thermal (native and wet) SiO2 interface in oxide–nitride–oxide structures are studied by using secondary ion mass spectroscopy, electron energy loss spectroscopy (EELS) and Auger electron spectroscopy (AES) measurements. EELS and AES experiments show the existence of excess silicon at the Si3N4/thermal SiO2 interface. Excess silicon (Si–Si bonds) at Si3N4/SiO2 interface exists in the form of Si-rich silicon oxynitride. Numerical simulation of the Si–Si bond’s electronic structure by using semiempirical quantum-chemical method (MINDO/3) shows that Si–Si defects act as either electron or hole traps. This result explains the abnormally large electron and hole capturing at this interface reported earlier.

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B. A. Zaitsev

Papers

Excess silicon at the silicon nitride/thermal oxide interface in oxide–nitride–oxide structures