A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-/spl mu/m CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH /spl Sigma/-/spl Delta/ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.

/pdf/a-27-mw-cmos-fractional-n-synthesizer-using-digital-4raqamn9c1.pdf

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing a fractional- synthesizer as the FMCW generator, the transmitter linearly modulates the carrier frequency across a range of 700 MHz. The receiver together with an external baseband processor detects the distance and relative speed by conducting an FFT-based algorithm. Millimeter-wave PA and LNA are incorporated on chip, providing sufficient gain, bandwidth, and sensitivity. Fabricated in 65-nm CMOS technology, this prototype provides a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2-V supply.

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology

A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom /spl Sigma/-/spl Delta/ synthesizer implemented in a 0.6 /spl mu/m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.

/pdf/a-modeling-approach-for-spl-sigma-spl-delta-fractional-n-11dhjv5aj5.pdf

A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis

This design integrates a 4/sup th/ order type-2 charge-pump PLL frequency synthesizer for the DCS-1800 system in a standard 0.4 /spl mu/m CMOS process without external components. The VCO uses an integrated hollow planar inductor, formed in the 2 metal levels available on a lowly-doped substrate. The coil has a symmetrical octagonal shape and size optimized using 2-D circular finite-element analysis. Skin effect and eddy current losses are minimized, and the quality factor is 8.6. VCO phase noise is -122.5 dBc/Hz at 600 kHz offset and tuning range is 20%.

SP 23.5: A Fully Integrated CMOS DCS-1800 Frequency Synthesizer

A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.

/pdf/a-wideband-2-4-ghz-delta-sigma-fractional-npll-with-1-mb-s-1qda1jn31a.pdf

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

Based on oversampling A/D conversion technology which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier, a CMOS integrated fractional-N divider is presented. A complete fractional-N phase locked loop (PLL) which was constructed utilizing only the CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator is discussed. The resulting PLL is shown to exhibit no fractional spurs. >

/pdf/a-multiple-modulator-fractional-divider-1e2yxt2cwu.pdf

B. Conley

Papers

A multiple modulator fractional divider