$$\\left[ {\\begin{array}{*{20}{c}} {10} \\\\ { - v{{a}^{{ - 1}}}1} \\\\ \\end{array} } \\right]\\left[ {\\begin{array}{*{20}{c}} {au} \\\\ {vb} \\\\ \\end{array} } \\right]\\left[ {\\begin{array}{*{20}{c}} {1 - {{a}^{{ - 1}}}u} \\\\ {01} \\\\ \\end{array} } \\right] = \\left[ {\\begin{array}{*{20}{c}} {a0} \\\\ {0b - v{{a}^{{ - 1}}}u} \\\\ \\end{array} } \\right]$$ \n \n(1.1) \n \nprovided a is regular.

Determinants and matrices. By A. C. Aitken. Pp. vii, 135. 4s. 6d. 1939. University Mathematical Texts, 1. (Oliver and Boyd)

A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

Test pattern compression for an integrated circuit test environment

A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

Method and apparatus for selectively compacting test responses

A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

This paper presents a novel methodology of designing generators and compactors of test data. The essence of the proposed approach is to use a set of transformations, which alters the structure of the conventional linear feedback shift registers (LFSRs) while preserving the transition function of the original circuits. It is shown that after applying the transition function preserving transformations in a certain order, the resultant circuits feature a significantly reduced the number of levels of XOR logic, minimized internal fanouts, and simplified circuit layout and routing, as compared to previous schemes based on external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial. Consequently, the proposed devices can operate at higher speeds than those of conventional solutions and become highly modular structures.

Ring generators - new devices for embedded test applications

A practical method is described to determine the modulo-2 feedback shift-register connections for producing advanced (or delayed) versions of a pseudorandom binary sequence.

B. Ireland

Papers

Matrix method to determine shift-register connections for delayed pseudorandom binary sequences