B.J. Benschneider

TL;DR: A six-issue, four-fetch, out-of-order execution, 6OOMHz Alpha microprocessor achieves an estimated 40SpecInt95, 60SpecFP95 and 1800MB/s on McCalpin Stream.

TL;DR: A new CMOS microprocessor, the Alpha 21164, reaches 1,200 mips/600 MFLOPS (peak performance) and this new implementation of the Alpha architecture achieves SPECint92/SPECfp92 performance of 345/505 (estimated).

TL;DR: A 300-MHz, custom 64-bit VLSI, second-generation Alpha CPU chip has been developed and can issue four instructions per cycle and delivers 1,200 mips/600 MFLOPS (peak).

TL;DR: A 6-way out-of-order issue custom VLSI implementation of the Alpha architecture runs at >1 GHz and contains two on-chip cache arrays; a 64 kB 2-way set associative instruction cache and 64 k B 2- way set Associative dual-ported data cache.

TL;DR: A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating- point operations and integer multiplication as defined by a superminicomputer architecture standard.