S
Sridhar Samudrala
Publications - 5
Citations - 131
Sridhar Samudrala is an academic researcher. The author has contributed to research in topics: Floating point & Operand. The author has an hindex of 5, co-authored 5 publications receiving 127 citations.
Papers
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Journal Article
A 200-MHz 64-bit Dual-Issue CMOS Microprocessor.
Daniel W. Dobberpuhl,Richard T. Witek,Randy L. Allmon,Robert Anglin,David Bertucci,Sharon M. Britton,Linda Chao,Robert A. Conrad,Daniel E. Dever,Bruce A. Gieseke,Soha Hassoun,Gregory W. Hoeppner,Kathryn Kuchler,Maureen Ladd,Burton M. Leary,Liam Madden,Edward J. McLellan,Derrick Robert Meyer,James Montanaro,Donald A. Priore,Vidya Rajagopalan,Sridhar Samudrala,Sribalan Santhanam +22 more
TL;DR: In this article, the authors propose a RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, which implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations.
Patent
Leading one/zero bit detector for floating point operation
TL;DR: In this article, a circuit is provided for using the input operands of a floating point addition or subtraction operation to detect the leading one or zero bit position in parallel with the arithmetic operation.
Patent
Method and apparatus for controlling a rounding operation in a floating point multiplier circuit
TL;DR: In this article, the sticky bit is calculated in a path separate from the multiply operation, so the n-2 least significant sums need not be calculated, which saves time and circuitry in an array multiplier.
Proceedings ArticleDOI
A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor
B.J. Benschneider,William J. Bowhill,Elizabeth M. Cooper,M.N. Gavrielov,Paul E. Gronowski,V.K. Maheshwari,V. Peng,J.D. Pickholtz,Sridhar Samudrala +8 more
TL;DR: A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating- point operations and integer multiplication as defined by a superminicomputer architecture standard.
Proceedings ArticleDOI
CMOS implementation of a 32 b computer
Randy L. Allmon,William J. Bowhill,B.J. Benschneider,J.F. Brown,Elizabeth M. Cooper,W.H. Durdan,A Fisher,M.N. Gavrielov,Paul E. Gronowski,W.J. Grundmann,W.V. Herrick,D. Kravitz,L. Madden,V.K. Maheshwari,R.C. Marcello,G.G. Mills,M. Mittal,V. Peng,J.D. Pickholtz,Sridhar Samudrala,D.E. Sanders,R.L. Stamm,P.J. Starvaski,W.R. Wheeler +23 more
TL;DR: A four-chip custom VLSI implementation of a 32-b computer comprised of a CPU, a secondary cache controller, a floating-point accelerator, and a clock generator is described, which operates at a cycle time of 28 ns and is compatible with an existing computer architecture.