Currently, Field Programmable Gate Array (FPGA) goes beyond the low-level line-by-line hardware description language programming in implementing parallel multidimensional image filtering algorithms. High-level abstract hardware-oriented parallel programming method can structurally bridge this gap. This paper proposes a first step toward such a method to efficiently implement Parallel 2-D MRI image filtering algorithms using the Xilinx system generator. The implementation method consists of five simple steps that provide fast FPGA prototyping for high performance computation to obtain excellent quality of results. The results are obtained for nine 2-D image filtering algorithms. Behaviourally, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are targeted to achieve; lower power consumption of (1.57 W) and down to (0.97 W) respectively at maximum sampling frequency of up to (230 MHZ). Then, one of the nine MRI image filtering algorithms, has empirically improved to generate an enhanced MRI image filtering with moderate lower power consumption at higher maximum frequency.

Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator

Contemporary underwater acoustic networks use low frequency modems. While these modems can provide long range communication, their low operating frequencies mean that only low channel bandwidth is available, which results in slow data rates. This motivates our development of a high frequency modem which offers the potential for large channel bandwidth, and hence greater link capacity. There is a range-frequency trade-off because absorption becomes very high at high frequency. Our intended operating frequencies from 100 kHz to 1 MHz would only support link ranges perhaps from 1 km down to under 100m, with communication ranges longer than this requiring forwarding over a network. Reconfigurable computing based Field Programmable Gate Arrays (FPGAs) are used to accelerate product development and support evolution of fielded systems. Given the immaturity of the field of underwater communication, a reconfigurable modem is a valuable tool for development and testing modem techniques. We present a design idea to implement an acoustic modem solely in FPGA, whereas most existing modems are implemented as a combination of FPGA and DSP processors. Aside from simple anti-aliasing filters, which could be incorporated in the preamplifier stage, the modem does all of its processing in the digital domain - maximising flexibility. In this work, we describe the initial design and architecture of our software based acoustic modem that avoids the monetary cost or time investment required to design a commercial modem or custom hardware for many applications. Our demodulator is implemented using a Costas loop which performs both suppressed carrier reconstruction and synchronous data detection within the loop. Results from initial implementation are also reported in this paper.

Design of a high frequency FPGA acoustic modem for underwater communication

Parallel 1-D signal filtering algorithm is implemented as a parameterized efficient FPGA-based architecture using Xilinx System Generator. The implemented algorithm is a linear indirect filters achieved by a parallel FFT/point-by-point complex inner product/ IFFT convolution unit array. The implemented architecture manifests a 38 % higher performance per Watt at maximum frequency. The parameterized implementation provides rapid system-level FPGA prototyping and operating frequency portability. Consequently, the results are obtained independent of the two targeted Virtex-6 FPGA boards, namely xc6vlX240Tl–1lff1759 and xc6vlX130Tl–1lff1156, to achieve lower power consumption of (1.6 W) and down to (0.99 W) respectively at a maximum frequency of up to (216 MHz). A case study of real-time speech filtering shows excellent performance results of power consumption down to (0.99W) at maximum frequency of up to (216 MHz).

Parameterized FPGA-based architecture for parallel 1-D filtering algorithms

Problem statement: Current Neuroimaging developments, in biological research and diagnostics, demand an edge-defined and noise-free MRI scans. Thus, this study presents a generalized parallel 2-D MRI filtering algorithm with their FPGA-based implementation in a single unified architecture. The parallel 2-D MRI filtering algorithms are Edge, Sobel X, Sobel Y, Sobel X-Y, Blur, Smooth, Sharpen, Gaussian and Beta (HYB). Then, the nine MRI image filtering algorithm, has empirically improved to generate enhanced MRI scans filtering results without significantly affecting the developed performance indices of high throughput and low power consumption at maximum operating frequency. Approach: The parallel 2-d MRI filtering algorithms are developed and FPGA implemented using Xilinx System Generator tool within the ISE 12.3 development suite. Two unified architectures are behaviorally developed, depending on the abstraction level of implementation. For performance indices comparison, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are behaviorally targeted. Results: The improved parallel 2-D filtering algorithms enhanced the filtered MRI scans to be edge-defined and noise free grayscale imaging. The single architecture is efficiently prototyped to achieve: high filtering performance of (11230 frames/second) throughput for 64*64 MRI grayscale scan, minimum power consumption of 0.86 Watt with a junction temperature of 52°C and a maximum frequency of up to (230 MHz). Conclusion: The improved parallel MRI filtering algorithms which are developed as a single unified architecture provide visibility enhancement within the filtered MRI scan to aid the physician in detecting brain diseases, e.g., trauma or intracranial haemorrhage. The high filtering throughput is feasibly nominee the nine parallel MRI filtering algorithms for applications such as real-time MRI potential future applications. Future Work: a set of parallel 3-D fMRI filtering algorithms will be investigated to be developed and fast FPGA prototyped for future research project.

FPGA-Based Architecture for a Generalized Parallel 2-D MRI Filtering Algorithm

FPGA implementation of image processing technique for blood samples characterization

Summary Quadrature Phase Shift Keying (QPSK) is the preferred modulation scheme for satellite data communication. A two stage estimation scheme for the demodulator for processing satellite data is proposed in this paper, where carrier frequency estimation is followed by timing recovery under training. Frequency offset estimation is performed by finding the slope of the best fit line through the unwrapped phase. Since this carrier frequency estimation technique gives an approximate estimate of the frequency offset, there still remains some frequency offset to be corrected. This is done in the second stage, where least mean square algorithm is employed to track the variations in frequency and estimating the symbols. Estimation of the correct sampling instant is based upon finding the minima of the absolute of the received training pattern and then calculating the maximum energy instant from it. An overview of the whole system architecture is presented and its performance is evaluated. BER curves for different frequency and timing offsets are also presented. Some tasks in the system may serve as bottlenecks to higher data rates owing to their computationally intensive nature. These tasks are identified and based upon that, the proposed algorithm is partitioned into two parts. One part is to be implemented on FPGA and consists of high computational complexity modules and the other is to be coded on a DSP processor.

/pdf/development-of-algorithm-for-demodulator-for-processing-21bnppo7jp.pdf

Development of Algorithm for Demodulator for Processing Satellite Data Communication

Summary This paper proposes a novel VLSI architecture for the demodulator for processing satellite data communication. The overall receiver algorithm is divided into two parts: one to be implemented on an FPGA and the other on a DSP processor. A new distributed arithmetic based architecture for implementing a Sampling Rate Converter is also proposed. The main advantage of this architecture is that it does not employ any MAC unit, whose operational speed is, generally, a bottleneck for high filter throughput. Instead, it makes extensive use of LUTs and hence is ideally suited for FPGA implementation. Architecture for Digital Frequency Synthesizer, which gives 60 dB spectral purity, is also presented. The developed FPGA core consists of a mixer and two numbers of 193 tap, RRC filters to accept modulated, 12-bit, signed ADC output at a sampling frequency of 1.536 MHz and convert it into In-phase (I) and Quadrature-phase (Q) channel outputs, each of size 16 bits, signed, at half the sampling frequency. The main design goals in this work were to maintain low system complexity and reduce power consumption and chip area requirements. These architectures were coded in Verilog HDL and implemented on Xilinx FPGA. The design was synthesized with XCV600-4 FPGA and occupies about 2360 slices with an equivalent gate count of about 45000 and operating at a maximum frequency of 19.8 MHz. The entire modulator and demodulator have been coded in Matlab in order to validate the hardware results. The hardware and MATLAB results compare favorably.

/pdf/development-of-algorithm-architecture-and-fpga-f9ojt7pn6x.pdf

Development of Algorithm, Architecture and FPGA Implementation of Demodulator for Processing Satellite Data Communication

This paper proposes a novel architecture for sampling rate converter of the demodulator for processing satellite data communication. The overall receiver algorithm is divided into two parts: one to be implemented on an FPGA and the other on a DSP processor. A new distributed arithmetic based architecture for implementing a Sampling Rate Converter is also proposed. The main advantage of this architecture is that it does not employ any MAC unit, whose operational speed is, generally, a bottleneck for high filter throughput. Instead, it makes extensive use of LUTs and hence is ideally suited for FPGA implementation. The main design goals in this work were to maintain low system complexity and reduce power consumption and chip area requirements.

B. S. Nagabushan

Papers

Development of Algorithm for Demodulator for Processing Satellite Data Communication

Development of Algorithm, Architecture and FPGA Implementation of Demodulator for Processing Satellite Data Communication

Design of Architecture for Sampling Rate Converter of Demodulator