Understanding a person's feelings is a very important process for the affective computing. People express their emotions in various ways. Among them, facial expression is the most effective way to present human emotional status. We propose efficient deep joint spatiotemporal features for facial expression recognition based on the deep appearance and geometric neural networks. We apply three-dimensional (3D) convolution to extract spatial and temporal features at the same time. For the geometric network, 23 dominant facial landmarks are selected to express the movement of facial muscle through the analysis of energy distribution of whole facial landmarks.We combine these features by the designed joint fusion classifier to complement each other. From the experimental results, we verify the recognition accuracy of 99.21%, 87.88%, and 91.83% for CK+, MMI, and FERA datasets, respectively. Through the comparative analysis, we show that the proposed scheme is able to improve the recognition accuracy by 4% at least.

https://www.mdpi.com/1424-8220/20/7/1936/pdf

Deep Joint Spatiotemporal Network (DJSTN) for Efficient Facial Expression Recognition.

Dustbins are containers used for collecting household waste all around the world. In our day to day life, we dispose variety of waste materials categorized as industrial waste, sewage wastes, domestic wastes etc. Dustbins are used for collecting the domestic waste materials. Indoor dustbins are used to collect wastes from household, which are then disposed into the outdoor dustbins maintained by the Corporation or Municipality. Indoor dustbins are smaller in size, whereas municipal dustbins present outdoors are so big in size since it has to accommodate all the wastes from many household users in that area. Hence our main focus is on the dustbins placed outside every corner in the streets in order to keep the environment clean. Road side dustbins are not monitored and cleaned properly most of the times. In this paper we propose a new system for managing garbage within Smart Cities. This Efficient Waste disposal or Management System is considered as an essential for Modern Smart Cities (MSC). Internet of Things (IoT) can be implemented both in IS and MSC creating an highly developed proposal for future Operations. Special methods can be applied to enhance technology used for high Quality of Service (QoS) in our waste management system. Specifically, IoT components like sensors, detectors, and actuators are integrated into Intelligent System (IS) and Inspection systems for efficient waste management. We recommend a sophisticated IS for efficient waste management in Smart Cities. The proposed system is an automated alert based smart bin or garbage collection system and to alert the authorities like corporation or local waste disposal team. Using this, we can monitor the complete waste disposal in an efficient way.

Efficient IOT Based Smart Bin for Clean Environment

Cucumber disease recognition based on Global-Local Singular value decomposition

Currently, Field Programmable Gate Array (FPGA) goes beyond the low-level line-by-line hardware description language programming in implementing parallel multidimensional image filtering algorithms. High-level abstract hardware-oriented parallel programming method can structurally bridge this gap. This paper proposes a first step toward such a method to efficiently implement Parallel 2-D MRI image filtering algorithms using the Xilinx system generator. The implementation method consists of five simple steps that provide fast FPGA prototyping for high performance computation to obtain excellent quality of results. The results are obtained for nine 2-D image filtering algorithms. Behaviourally, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are targeted to achieve; lower power consumption of (1.57 W) and down to (0.97 W) respectively at maximum sampling frequency of up to (230 MHZ). Then, one of the nine MRI image filtering algorithms, has empirically improved to generate an enhanced MRI image filtering with moderate lower power consumption at higher maximum frequency.

Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator

The issue of brain magnetic resonance image exploration together with classification receives a significant awareness in recent years. Indeed, various computer-aided-diagnosis solutions were suggested to support radiologist in decision-making. In this circumstance, adequate image classification is extremely required as it is the most common critical brain tumors which often develop from subdural hematoma cells, which might be common type in adults. In healthcare milieu, brain MRIs are intended for identification of tumor. In this regard, various computerized diagnosis systems were suggested to help medical professionals in clinical decision-making. As per recent problems, Neuroendoscopy is the gold standard intended for discovering brain tumors; nevertheless, typical Neuroendoscopy can certainly overlook ripped growths. Neuroendoscopy is a minimally-invasive surgical procedure in which the neurosurgeon removes the tumor through small holes in the skull or through the mouth or nose. Neuroendoscopy enables neurosurgeons to access areas of the brain that cannot be reached with traditional surgery to remove the tumor without cutting or harming other parts of the skull. We focused on finding out whether or not visual images of tumor ripped lesions ended up being much better by auto fluorescence image resolution as well as narrow-band image resolution graphic evaluation jointly with the latest neuroendoscopy technique. Also, within the last several years, pathology labs began to proceed in the direction of an entirely digital workflow, using the electronic slides currently being the key element of this technique. Besides lots of benefits regarding storage as well as exploring capabilities with the image information, among the benefits of electronic slides is that they can help the application of image analysis approaches which seek to develop quantitative attributes to assist pathologists in their work. However, systems also have some difficulties in execution and handling. Hence, such conventional method needs automation. We developed and employed to look for the targeted importance along with uncovering the best-focused graphic position by way of aliasing search method incorporated with new Neuroendoscopy Adapter Module (NAM) technique.

/pdf/neuroendoscopy-adapter-module-development-for-better-brain-2rv2ao7o7j.pdf

Neuroendoscopy Adapter Module Development for Better Brain Tumor Image Visualization

Facial feature tracking and facial actions recognition from image sequence attracted great attention in computer vision field Computational facial expression analysis is a challenging research topic in computer vision It is required by many applications such as human-computer interaction, computer graphic animation and automatic facial expression recognition In recent years, plenty of computer vision techniques have been developed to track or recognize the facial activities in three levels First, in the bottom level, facial feature tracking, which usually detects and tracks prominent landmarks surrounding facial components (ie, mouth, eyebrow, etc), captures the detailed face shape information; Second, facial actions recognition, ie, recognize facial action units (AUs) defined in FACS, try to recognize some meaningful facial activities (ie, lid tightener, eyebrow raiser, etc); In the top level, facial  expression analysis attempts to recognize some meaningful facial activities (ie, lid tightener, eyebrow raiser, etc); In the top level, facial expression analysis attempts to recognize facial expressions that represent the human emotion states In this proposed algorithm initially detecting eye and mouth, features of eye and mouth are extracted using Gabor filter, (Local Binary Pattern) LBP and PCA is used to reduce the dimensions of the features Finally SVM is used to classification of expression and facial action units

/pdf/facial-expression-recognition-using-svm-classifier-4dkt0bnibv.pdf

Facial Expression Recognition Using SVM Classifier

The method of connecting the objects or things through wireless connectivity, Internet called Internet Of Things. Nowadays a variety of tasks are based on IOT. Cities in the world are becoming smarter by implementing the things around using IOT. This is a new trend in technology. Smart cities include obstacle tracking, object sensing, traffic control, tracking of our activities, examining the baby, monitoring home lights and so on. One of the objective of smart cities is keeping the environment clean and neat. This aim is not fulfilled without the garbage bin management system. Hence the paper “IOT Based Intelligent Bin for Smart Cities” has been developed. Bin management is one of the major applications of IOT. Here sensors are connected to the all the bins at different areas. It senses the level of garbage in bin. When it reaches threshold a message is sent via GSM to the concerned person to clean it as soon as possible. The completed task is done in LabVIEW environment.

https://ijritcc.org/index.php/ijritcc/article/download/2159/2159

IOT Based Intelligent Bin for Smart Cities

Summary Quadrature Phase Shift Keying (QPSK) is the preferred modulation scheme for satellite data communication. A two stage estimation scheme for the demodulator for processing satellite data is proposed in this paper, where carrier frequency estimation is followed by timing recovery under training. Frequency offset estimation is performed by finding the slope of the best fit line through the unwrapped phase. Since this carrier frequency estimation technique gives an approximate estimate of the frequency offset, there still remains some frequency offset to be corrected. This is done in the second stage, where least mean square algorithm is employed to track the variations in frequency and estimating the symbols. Estimation of the correct sampling instant is based upon finding the minima of the absolute of the received training pattern and then calculating the maximum energy instant from it. An overview of the whole system architecture is presented and its performance is evaluated. BER curves for different frequency and timing offsets are also presented. Some tasks in the system may serve as bottlenecks to higher data rates owing to their computationally intensive nature. These tasks are identified and based upon that, the proposed algorithm is partitioned into two parts. One part is to be implemented on FPGA and consists of high computational complexity modules and the other is to be coded on a DSP processor.

/pdf/development-of-algorithm-for-demodulator-for-processing-21bnppo7jp.pdf

Development of Algorithm for Demodulator for Processing Satellite Data Communication

Summary This paper proposes a novel VLSI architecture for the demodulator for processing satellite data communication. The overall receiver algorithm is divided into two parts: one to be implemented on an FPGA and the other on a DSP processor. A new distributed arithmetic based architecture for implementing a Sampling Rate Converter is also proposed. The main advantage of this architecture is that it does not employ any MAC unit, whose operational speed is, generally, a bottleneck for high filter throughput. Instead, it makes extensive use of LUTs and hence is ideally suited for FPGA implementation. Architecture for Digital Frequency Synthesizer, which gives 60 dB spectral purity, is also presented. The developed FPGA core consists of a mixer and two numbers of 193 tap, RRC filters to accept modulated, 12-bit, signed ADC output at a sampling frequency of 1.536 MHz and convert it into In-phase (I) and Quadrature-phase (Q) channel outputs, each of size 16 bits, signed, at half the sampling frequency. The main design goals in this work were to maintain low system complexity and reduce power consumption and chip area requirements. These architectures were coded in Verilog HDL and implemented on Xilinx FPGA. The design was synthesized with XCV600-4 FPGA and occupies about 2360 slices with an equivalent gate count of about 45000 and operating at a maximum frequency of 19.8 MHz. The entire modulator and demodulator have been coded in Matlab in order to validate the hardware results. The hardware and MATLAB results compare favorably.

/pdf/development-of-algorithm-architecture-and-fpga-f9ojt7pn6x.pdf

Development of Algorithm, Architecture and FPGA Implementation of Demodulator for Processing Satellite Data Communication

Due to high rise in demand for video processing on hardware FPGA implementation of various image processing algorithm has become a necessity. Lot of research work is being done in the field of image processing and video processing on FPGA. In this paper we specifically concentrate on working Background identification, moving object detection and tracking. Keeping in mind the previous work dons in this area we have selected Gaussian mixture model for the implementation. The main work carried out by Gaussian mixture model is to is a common feature in many video processing systems. The paper speaks about two block of implementation mainly the image block generation and the RGB to YCbCr conversion. It has been proved from the design that it is efficient for high definition (HD) video sequences with frame size 1920 × 1080. Both the bocks are targeted on commercial field-programmable gate-array (FPGA) devices. When implemented on Atrix7 100t it uses 3% of FPGA logic resources. The second block takes like 2% of the FPGA resource. The total time required to process single frame is less than 2ns.

K. R. Nataraj

Papers

Facial Expression Recognition Using SVM Classifier

IOT Based Intelligent Bin for Smart Cities

Development of Algorithm for Demodulator for Processing Satellite Data Communication

Development of Algorithm, Architecture and FPGA Implementation of Demodulator for Processing Satellite Data Communication

FPGA Implementation of Image Block Generation and Color Space Conversion for the Gaussian Mixture Model