Resistance random access memories (RRAM) or memristors with an analog change of conductance are widely explored as an artificial synapse, e.g., Pr0.7Ca0.3MnO3 (PCMO) RRAM-based synapses. In addition to synapses, scaled neurons are essential to enable a neuromorphic hardware. In this letter, we propose a PCMO RRAM for integrate and fire (IF) neuron. The analog conductance increase during SET process enables integration function. Upon exceeding a conductance threshold (i.e., fire) during a READ operation, a hard RESET is performed to reduce the conductance. The SET, READ, and RESET are performed in different phases of a clock to enable a PCMO for IF neuron. The availability of a non-volatile PCMO-based synapse makes PCMO for IF neuron attractive. Finally, PCMO-based neuron in spiking neural network yields software-equivalent classification accuracy as demonstrated on standard Fischer’s Iris flower data set.

PCMO RRAM for Integrate-and-Fire Neuron in Spiking Neural Networks

Recent advances in memristor technology lead to the feasibility of large-scale neuromorphic systems by leveraging the similarity between memristor devices and synapses For instance, memristor cross-point arrays can realize dense synapse network among hundreds of neuron circuits, which is not affordable for traditional implementations However, little progress was made in synapse designs that support both static and dynamic synaptic properties In addition, many neuron circuits require signals in specific pulse shape, limiting the scale of system implementation Last but not least, a bottom-up study starting from realistic memristor devices is still missing in the current research of memristor-based neuromorphic systems Here, we propose a memristor-based dynamic (MD) synapse design with experiment-calibrated memristor models The structure obtains both static and dynamic synaptic properties by using one memristor for weight storage and the other as a selector We overcame the device nonlinearities and demonstrated spike-timing-based recall, weight tunability, and spike-timing-based learning functions on MD synapse Furthermore, a temporal pattern learning application was investigated to evaluate the use of MD synapses in spiking neural networks, under both spike-timing-dependent plasticity and remote supervised method learning rules

A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks

Various Threshold Switching Devices for Integrate and Fire Neuron Applications

As we approach the end of the silicon road map, alternative computing models that can solve at-scale problems in the data-centric world are becoming important. This is accompanied by the realization that binary abstraction and Boolean logic, which have been the foundations of modern computing revolution, fall short of the desired performance and power efficiency. In particular, hard computing problems relevant to pattern matching, image and signal processing, optimizations, and neuromorphic applications require alternative approaches. In this paper, we review recent advances in oscillatory dynamical system-based models of computing and their implementations. We show that simple configurations of oscillators connected using simple electrical circuits can result in interesting phase and frequency dynamics of such coupled oscillatory systems. Such networks can be controlled, programmed, and observed to solve computationally hard problems. Although our discussion in this paper is limited to insulator-to-metal transition devices and spin-torque oscillators, the general philosophy of such a computing paradigm of “let physics do the computing” can be translated to other mediums as well, including micromechanical and optical systems. We present an overview of the mathematical treatments necessary to understand the time evolution of these systems and highlight the recent experimental results in this area that suggest the potential of such computational models.

Computing With Networks of Oscillatory Dynamical Systems

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursued approaches to achieve such a subthermionic subthreshold swing consist in alternative carrier injection mechanisms, like quantum mechanical band-to-band tunneling (BTBT) in Tunnel FETs or abrupt phase-change in metal-insulator transition (MIT) devices. The strengths of the BTBT and MIT have been combined in a hybrid device architecture called phase-change tunnel FET (PC-TFET), in which the abrupt MIT in vanadium dioxide (VO2) lowers the subthreshold swing of strained-silicon nanowire TFETs. In this work, we demonstrate that the principle underlying the low swing in the PC-TFET relates to a sub-unity body factor achieved by an internal differential gate voltage amplification. We study the effect of temperature on the switching ratio and the swing of the PC-TFET, reporting values as low as 4.0 mV/decade at 25 °C, 7.8 mV/decade at 45 °C. We discuss how the unique characteristics of the PC-TFET open new perspectives, beyond FETs and other steep-slope transistors, for low power electronics, analog circuits and neuromorphic computing.

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor.

High power consumption has significantly increased the cooling cost in high-performance computation stations and limited the operation time in portable systems powered by batteries. Traditional power reduction mechanisms have limited traction in the post-Dennard Scaling landscape. Emerging research on new computation devices and associated architectures has shown three trends with the potential to greatly mitigate current power limitations. The first is to employ steep-slope transistors to enable fundamentally more efficient operation at reduced supply voltage in conventional Boolean logic, reducing dynamic power. The second is to employ brain-inspired computation paradigms, directly embodying computation mechanisms inspired by the brains, which have shown potential in extremely efficient, if approximate, processing with silicon-neuron networks. The third is “let physics do the computation”, which focuses on using the intrinsic operation mechanism of devices (such as coupled oscillators) to do the approximate computation, instead of building complex circuits to carry out the same function. This paper first describes these three trends, and then proposes the use of the hybrid-phase-transition-FET (Hyper-FET), a device that could be configured as a steep-slope transistor, a spiking neuron cell, or an oscillator, as the device of choice for carrying these three trends forward. We discuss how a single class of device can be configured for these multiple use cases, and provide in-depth examination and analysis for a case study of building coupled-oscillator systems using Hyper-FETs for image processing. Performance benchmarking highlights the potential of significantly higher energy efficiency than dedicated CMOS accelerators at the same technology node.

Enabling New Computation Paradigms with HyperFET - An Emerging Device

Spiking neural networks are expected to play a vital role in realizing ultra-low power hardware for computer vision applications [1]. While the algorithmic efficiency is promising, their solid-state implementation with traditional CMOS transistors lead to area expensive solutions. Transistors are typically designed and optimized to perform as switches and do not naturally exhibit the dynamical properties of neurons. In this work, we harness the abrupt insulator-to-metal transition (IMT) in a prototypical IMT material, vanadium dioxide (VO 2 ) [2], to experimentally demonstrate a compact integrate and fire spiking neuron [3]. Further, we show multiple spiking dynamics of the neuron relevant to implementing ‘winner take all’ max pooling layers employed in image processing pipelines.

Baihua Xie

Papers

Enabling New Computation Paradigms with HyperFET - An Emerging Device

Phase transition oxide neuron for spiking neural networks