Ben Feinberg

TL;DR: A new error correction scheme for analog neural network accelerators based on arithmetic codes that reduces the respective misclassification rates by 1.5x and 1.1x and encodes the data through multiplication by an integer, which preserves addition operations through the distributive property.

TL;DR: This work explores and consolidates the various approaches that have been proposed to address the critical challenges faced by analog accelerators, for both neural network inference and training, and highlights the key design trade-offs underlying these techniques.

TL;DR: This paper presents the first proposal to enable scientific computing on memristive crossbars, and three techniques are explored — reducing overheads by exploiting exponent range locality, early termination of fixed-point computation, and static operation scheduling — that together enable a fixed- Point Memristive accelerator to perform high-precision floating point without the exorbitant cost of naïve floating-point emulation on fixed-pointers.

TL;DR: The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin–orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component.

TL;DR: In this article, the authors examine the damage caused by device-level noise and retention issues, introduce a mitigation strategy, and demonstrate its use in fabricated array of SONOS (Silicon Oxide-Nitride-Oxide-Silicon) devices.