IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 

About: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits is an academic journal published by Institute of Electrical and Electronics Engineers. The journal publishes majorly in the area(s): Computer science & Artificial neural network. It has an ISSN identifier of 2329-9231. It is also open access. Over the lifetime, 142 publications have been published receiving 2355 citations. The journal is also known as: JXCDC & IJESQ5.

Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits

Abstract: A new benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented. It includes new devices with ferroelectric, straintronic, and orbitronic computational state variables. Standby power treatment and memory circuits are included. The set of circuits is extended to sequential logic, including arithmetic logic units. The conclusion that tunneling field-effect transistors are the leading low-power option is reinforced. Ferroelectric transistors may present an attractive option with faster switching delay. Magnetoelectric effects are more energy efficient than spin transfer torque, but the switching speed of magnetization is a limitation. This article enables a better focus on promising beyond-CMOS exploratory devices.

Tunnel Field-Effect Transistors in 2-D Transition Metal Dichalcogenide Materials

Abstract: In this paper, the performance of tunnel field-effect transistors (TFETs) based on 2-D transition metal dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of TFETs is their low ON-currents. 2-D material-based TFETs can have tight gate control and high electric fields at the tunnel junction, and can, in principle, generate high ON-currents along with a subthreshold swing (SS) smaller than 60 mV/decade. Our simulations reveal that high-performance TMD TFETs not only require good gate control, but also rely on the choice of the right channel material with optimum bandgap, effective mass, and source/drain doping level. Unlike previous works, a full-band atomistic tight-binding method is used self-consistently with 3-D Poisson equation to simulate ballistic quantum transport in these devices. The effect of the choice of the TMD material on the performance of the device and its transfer characteristics are discussed. Moreover, the criteria for high ON-currents are explained with a simple analytic model, showing the related fundamental factors. Finally, the SS and energy delay of these TFETs are compared with conventional CMOS devices.

Coupled-Oscillator Associative Memory Array Operation for Pattern Recognition

Abstract: The operation of an array of coupled oscillators underlying the associative memory function is demonstrated for various interconnection topologies (cross-connect and star-coupled). Three types of nonlinear oscillators (Andronov–Hopf, phase-locked loop, and spin torque) and their synchronization behavior are compared. Frequency-shift keying scheme of encoding input and memorized data is introduced. The speed of synchronization of oscillators and the evolution of the degree of match are studied as a function of device parameters.

Sub- kT/q Switching in Strong Inversion in PbZr 0.52 Ti 0.48 O 3 Gated Negative Capacitance FETs

Abstract: Hysteretic switching with a sub- kT/q steep slope (13 mV/decade at room temperature) is experimentally demonstrated in MOSFETs with PbZr0.52 Ti0.48O3 as a ferroelectric (FE) gate insulator, integrated on a silicon channel with a nonperovskite high- k dielectric (HfO2) as a buffer interlayer. The steep switching is independent of drain bias. For the first time, sub- kT/q switching due to FE negative capacitance is observed not at low currents, but in strong inversion ( ${I}_{d}\sim $ 100 $\mu \text{A}/\mu \text{m}$ ). Steep switching in strong inversion provides an important point of consistency with the predictions of the Landau–Devonshire theory and the Landau–Khalatnikov equation.

Polarization-Engineered III-Nitride Heterojunction Tunnel Field-Effect Transistors

Abstract: The concept and simulated device characteristics of tunneling field-effect transistors (TFETs) based on III-nitride heterojunctions are presented for the first time. Through polarization engineering, interband tunneling can become significant in III-nitride heterojunctions, leading to the potential for a viable TFET technology. Two prototype device designs, inline and sidewall-gated TFETs, are discussed. Polarization-assisted p-type doping is used in the source region to mitigate the effect of the deep Mg acceptor level in p-type GaN. Simulations indicate that TFETs based on III-nitride heterojunctions can be expected to achieve ON/ OFF ratios of $10^{6}$ or more, with switching slopes well below 60 mV/decade, ON-current densities approaching 100 $\mu \text{A}/\mu \text{m}$ , and energy delay products as low as 67 aJ-ps/ $\mu \text{m}$ .