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Benno Koeppl
Researcher at Infineon Technologies
Publications - 27
Citations - 194
Benno Koeppl is an academic researcher from Infineon Technologies. The author has contributed to research in topics: Voltage & Signal. The author has an hindex of 7, co-authored 27 publications receiving 188 citations.
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Patent
Circuit arrangement including a multi-level converter
TL;DR: In this article, a circuit includes voltage supply terminals configured to provide an AC output voltage, at least two converter units, and a control circuit, each converter unit includes input terminals including an electrical charge storage unit, output terminals and a switch arrangement connected between the input and output terminals.
Patent
Circuit arrangement for driving transistors in bridge circuits
Karl-Josef Martin,Markus Zannoth,Karl-Dieter Hein,Matthias Bogus,Mathias Von Borcke,Benno Koeppl +5 more
TL;DR: In this paper, a half-bridge with a highside switch and a low-side switch, each switch including a control terminal and a load path, is coupled in series between terminals for a supply potential and a terminal for a reference potential.
Proceedings ArticleDOI
EMC and switching loss improvement for fast switching power stages by di/dt, dv/dt optimization with 10ns variable current source gate driver
TL;DR: This work utilizes a monolithic current mode gate driver with a variable output current that can be changed within 10ns and confirmed to be as important as the dv/dt transition in the power MOSFET.
Patent
Schaltungsanordnung mit einem Mehrstufenwandler
TL;DR: Beschrieben wird eine Schaltungsanordnung mit einem Mehrstufenwandler, der aufweist: Spannungsversorgungsklemmen (11, 12), die dazu ausgebildet sind, eine Ausgangswechselspannung (Vac) bereitzustellen; wenigstens zwei Wandlerstufens (C1, C2, Cn), wet.
Proceedings ArticleDOI
10ns Variable current gate driver with control loop for optimized gate current timing and level control for in-transition slope shaping
TL;DR: In this article, a gate driver with variable output current capability is presented, where the gate driver can influence the di/dt and dv/dt transition separately and optimize whichever transition promises the highest improvement while keeping switching losses low.