Showing papers by "Bernhard Scholz published in 2003"

Code Instruction Selection Based on SSA-Graphs

Abstract: Instruction selection for embedded processors is a challenging problem. Embedded system architectures feature highly irregular instruction sets and complex data paths. Traditional code generation techniques have difficulties to fully utilize the features of such architectures and typically result in inefficient code.

Graph Coloring vs. Optimal Register Allocation for Optimizing Compilers

Abstract: Optimizing compilers play an important role for the efficient execution of programs written in high level programming languages. Current microprocessors impose the problem that the gap between processor cycle time and memory latency increases. In order to fully exploit the potential of processors, nearly optimal register allocation is of paramount importance. In the predominance of the x86 architecture and in the increased usage of high-level programming languages for embedded systems peculiarities and irregularities in their register sets have to be handled. These irregularities makes the task of register allocation for optimizing compilers more difficult than for regular architectures and register files. In this article we show how optimistic graph coloring register allocation can be extended to handle these irregularities. Additionally we present an exponential algorithm which in most cases can compute an optimal solution for register allocation and copy elimination. These algorithms are evaluated on a virtual processor architecture modeling two and three operand architectures with different register file sizes. The evaluation demonstrates that the heuristic graph coloring register allocator comes close to the optimal solution for large register files, but performs badly on small register files. For small register files the optimal algorithm is fast enough to replace a heuristic algorithm.

Advanced symbolic analysis for compilers

Abstract: syntax, 120 algebraic sum, 66 algorithm – algebraic sum, 66 – lower and upper bound, 56 – symbolic sum, 63, 64, 73 algorithm:simplify constraints, 68 application – large-scale, 79 array, 25 – algebra, 25 – block-wise distributed, 82 – distributed, 81 – multi-dimensional, 32 – one-dimensional, 25 – overlap area, 82 – privatization, 10 assignment, 14 associativity, 3 back edges, 118 benchmark – BDNA, 94 – Genesis benchmark suites, 93 – HNS, 94 – MDG, 94 – MG3D, 94 – OCEAN, 94 – PDE2, 94 – Perfect Benchmarks, 93, 96 – RiCEPS, 93 – TRACK, 94 – TRFD, 94 BNF – Backus Naur Form, 120 boundary condition, 22 CFG, 118 closed forms, 4 codes – FTRVMT, 75 communication – aggregation, 89 – coalescing, 89 – vectorization, 88 commutativity, 3 computer – cluster, 79 – control mechanism, 79 – distributed memory, 79 – distributed memory multiprocessing system DMMP, 80 – high performance, 79 – interconnection network, 79 – local memory, 79 – memory organization, 79 – MIMD, 79 – non-uniform memory access NUMA, 80 – shared memory, 79 – SIMD, 79 – SISD, 79 – uniform memory access UMA, 80 – virtual shared memory, 79 computer algebra systems – CAS, VIII computer language – semantics, 120 – syntax, 120 concept comprehension, 8 conditional statements – if-statement, 17 confluence, 18 constraints, 9

Addressing mode selection

Abstract: Many processor architectures provide a set of addressing modes in their address generation units. For example DSP (digital signal processors) have powerful addressing modes for efficiently implementing numerical algorithms. Typical addressing modes of DSP are auto post-modification and indexing for address registers. The selection of the optimal addressing modes in the means of minimal code size and minimal execution time depends on many parameters and is NP complete in general. In this work we present a new approach for solving the addressing mode selection (AMS) problem. We provide a method for modeling the target architecture's addressing modes as cost functions for a partitioned Boolean quadratic optimization problem (PBQP). For solving the PBQP we present an efficient and effective way to implement large matrices for modeling the cost model. We have integrated the addressing mode selection with the Atair C-Compiler for the uPD7705x DSP from NEC. In our experiments we show that the addressing mode selection can be optimally solved for almost all benchmark programs and the compile-time overhead of the address mode selection is within acceptable bounds for a production DSP compiler.

Partial Redundancy Elimination with Predication Techniques

Abstract: Partial redundancy elimination (PRE) techniques play an important role in optimizing compilers. Many optimizations, such as elimination of redundant expressions, communication optimizations, and load-reuse optimizations, employ PRE as an underlying technique for improving the efficiency of a program.

Busy wait analysis

Abstract: A busy wait loop is a loop which repeatedly checks whether an event occurs. Busy wait loops for process synchronization and communication are considered bad practice because (1) system failures may occur due to race conditions and (2) system resources are wasted by busy wait loops. In general finding a busy wait loop is an undecidable problem. To get a handle on the problem, we introduce a decidable predicate for loops that will spot most important classes of busy waiting although false alarms may occur. The loop predicate for detecting busy wait loops is based on control flow graph properties (such as loops) and program analysis techniques.

Predicated Partial Redundancy Elimination using a Cost Analysis

Abstract: Partial redundancy elimination (PRE) is a key technology for modern compilers. However traditional approaches are conservative and fail to exploit many opportunities for optimization. New PRE approaches which greatly increase the number of eliminated redundancies have been developed. However, they either cause the code size to explode or they cannot handle statements with side-effects. In this paper we describe a predicated partial redundancy elimination (PPRE) approach which can potentially remove all partial redundancies. To avoid performance overheads caused by predication, PPRE is applied selectively based on a cost model. The cost analysis presented in the paper utilizes probabilistic data-flow information to decide whether PPRE is profitable for each instance of a partially redundant computation. Refinements of the basic PPRE transformation are described in detail. In contrast to some other approaches our transformation is strictly semantics preserving.