A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Vertical system integration

A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

High-voltage transistor with multi-layer conduction region

A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

High-voltage lateral transistor with a multi-layered extended drain structure

An erasable programmable read only memory (EPROM) integrated circuit device 2 having a topside passivation layer 9 of silicon nitride which is transparent to ultraviolet radiation is disclosed. The refractive index of the silicon nitride film is in the range of 1.93±0.03.

Eprom with ultraviolet radiation transparent silicon nitride passivation layer

A method is described for producing an integrated circuit structure, including EPROMS, having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of voids in an underlying metal layer in the structure, and, in the case of EPROMS, maintaining sufficient UV light transmissity to permit erasure which comprises stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer to inhibit the formation of voids therein by implanting the metal layer with ions to change the grain structure adjacent the surface of the metal layer; forming an insulating intermediate layer between said the layer and the silicon nitride layer selected from the class consisting of an oxide of silicon and silicon oxynitride having a compressive/tensile stress which sufficiently compensates for the compressive stress of the silicon nitride layer; and controlling the compressive stress in the silicon nitride layer to provide resistance to moisture and ion penetration superior to silicon dioxide or silicon oxynitride layers of similar thickness while inhibiting formation of voids in the metal layer.

Passivation for integrated circuit structures

The ratio of silane-to-ammonia in a reaction designed to deposit a silicon nitride thin film affects the refractive index as well as the absorption coefficient of the film. By controlling the influx of these gases such that an essentially small ratio of silane-to-ammonia exists in a reaction chamber, a silicon nitride film 9 is deposited which is transparent to ultraviolet radiation 4. The exact ratio needed is dependent upon the geometry and operating parameters of the reaction chamber system employed in the deposition process. Ultraviolet light transparent silicon nitride film provides a superior passivation layer 9 for erasable programmable read only memory integrated devices 2.

Method of forming a silicon nitride film transparent to ultraviolet radiation and resulting article

A system is disclosed for producing an integrated circuit structure, including EPROMS, having excell­ent resistance to penetration by moisture and ion contaminants and a substantial absence of voids in an underlying metal layer in the structure, and, in the case of EPROMS, maintaining sufficient UV light transmissity to permit erasure which comprises stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer to inhibit the formation of voids therein by implanting the metal layer with ions to change the grain structure adja­cent the surface of the metal layer; forming an insulating intermediate layer between said the layer and the silicon nitride layer selected from the class consisting of an oxide of silicon and silicon oxynitride having a compressive/tensile stress which sufficiently compensates for the com­pressive stress of the silicon nitride layer; and controlling the compressive stress in the silicon nitride layer to provide resistance to moisture and ion penetration superior to silicon dioxide or silicon oxynitride layers of similar thickness while inhibiting formation of voids in the metal layer.

Improved passivation for integrated circuit structures

The ratio of silane-to-ammonia in a reaction designed to deposit a silicon nitride thin film affects the refractive index as well as the absorption coefficient of the film By controlling the influx of these gases such that an essentially small ratio of silane-to-ammonia exists in a reaction chamber, a silicon nitride film (9) is deposited which is transparent to ultraviolet radiation 4 The exact ratio needed is dependent upon the geometry and operating parameters of the reaction chamber system employed in the deposition process Ultraviolet light transparent silicon nitride film provides a superior passivation layer (9) for erasable programmable read only memory integrated devices (2)

Bert L. Allen

Papers

Eprom with ultraviolet radiation transparent silicon nitride passivation layer

Passivation for integrated circuit structures

Method of forming a silicon nitride film transparent to ultraviolet radiation and resulting article

Improved passivation for integrated circuit structures

Silicon nitride films for integrated circuits