VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

Delay fault test application via enhanced scan and skewed load techniques is shown to allow scan-based delay tests to be applied that are unrealizable in normal operation. Rather than higher coverage being a positive feature, it is shown to have negative impact on yield and designer productivity. The use of functionally justified tests is defended by both a motivating example and data from benchmark circuits. Implications on overhead, yield, timing optimization, and test debug are discussed.

Too much delay fault coverage is a bad thing

Skewed-load transition test is a form of scan-based transition test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. In the skewed-load test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the one that launches the transition) is required to be the next (i.e., one-bit-shift) pattern in the scan chain. Although a skewed-load transition test is attractive from a timing point of view, there are various problems that may arise if this strategy is used. Here, several issues of skewed-load transition test are investigated. Issues such as transition test calculus, detection probability of transition faults, transition fault coverage, and enhancement of transition test quality are thoroughly studied. >

Scan-based transition test

The implications of the observation that the probability of the occurrence of a transition on a wire of a circuit affects both the average power dissipation and the random pattern testability of a circuit are investigated. It is shown that restructuring a logic circuit can significantly affect its average power dissipation. Various methods for the synthesis of combinational logic networks are presented and the effect of different algorithms on the power dissipation of the circuit is demonstrated. The dual problem of improving the random pattern testability of logic circuits is emphasized. It is shown that modifying the signal probabilities can significantly affect the random pattern testability of a circuit. >

On average power dissipation and random pattern testability of CMOS combinational logic networks

As CAD tools become more sophisticated, they can synthesize logic networks that more nearly optimize the circuit area resources to maximize operating speeds. In this work we show, through formal arguments, that the path delays in such optimized networks will follow a more compact distribution and, in the extreme in some networks, will all be equal to the maximum delay through the network (cycle time). The impact of this type of synthesized network on delay testing will be shown and compared to the case for nonoptimized designs. Finally, recommendations will be made on how network timing optimization can be done in such a way as to minimize the adverse impact on product yield.

The interdependence between delay-optimization of synthesized networks and testing

Fastpath generates non-robust, robust or single-path-sensitization hazard-free robust path-delay tests for standard scan designs including high-impedance elements and functionally-described blocks. Results show effective and memory-efficient operation.

Fastpath: a path-delay test generator for standard scan designs

As electronic CAD synthesis tools become more powerful, they will increasingly refine delay measiirements and adjust path delays so as to increase the clock rate or to reduce the chip area. This paper discusses the implications of such events on testing for delay defects. We provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Finally, we discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults.

Delay Testing Quality in Timing-Optimized Designs

This work refines a statistical approach to the evaluation of testability algorithms, by: 1) using a more sensitive measure of correlation between testability measure and ease of fault detection, 2) adopting the proportion of test patterns that detected a fault as the measure of actual ease of detection, and 3) using a multiple correlation/regression approach that determines the optimal weighting of controllability and observability.

Results indicate a moderate correlation between SCOAP testability and fault detection proportion (approx .. 5), higher than previously found in such approaches but still low enough to indicate substantial room for improvement in the prediction provided by testability measures. In addition, the sum of controllability and observability predicts the results of fault detection almost as well as the optimal linear combination of the two.

Bill Underwood

Papers

The interdependence between delay-optimization of synthesized networks and testing

Fastpath: a path-delay test generator for standard scan designs

Delay Testing Quality in Timing-Optimized Designs

Correlating testability with fault detection

Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm.