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Biplab Roy

Researcher at West Bengal University of Technology

Publications -  11
Citations -  86

Biplab Roy is an academic researcher from West Bengal University of Technology. The author has contributed to research in topics: Sequential logic & Computer science. The author has an hindex of 5, co-authored 9 publications receiving 50 citations.

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Journal ArticleDOI

MoDTRAP: Improved heart rate tracking and preprocessing of motion-corrupted photoplethysmographic data for personalized healthcare

TL;DR: The proposed MoDTRAP technique provides noticeable improvements, separately, over existing methods on HR tracking and MA reduction and can be utilized for ambulatory healthcare monitoring.
Proceedings ArticleDOI

Design of a Coffee Vending Machine Using Single Electron Devices: (An Example of Sequential Circuit Design)

TL;DR: In this article, an implementation technique for sequential circuit using single electron tunneling technology (SET-s) with the example of designing of a "coffee vending machine" with the goal of getting low power and faster operation.
Journal ArticleDOI

On-Device Reliability Assessment and Prediction of Missing Photoplethysmographic Data Using Deep Neural Networks

TL;DR: An on-device reliability assessment from PPG measurements using a stack denoising autoencoder (SDAE) and multilayer perceptron neural network (MLPNN), which achieves over 95% accuracy for identifying acceptable PPG beats out of total 5000 using expert annotated data.
Journal ArticleDOI

i -PRExT: Photoplethysmography Derived Respiration Signal Extraction and Respiratory Rate Tracking Using Neural Networks

TL;DR: In this article, an ensemble empirical mode decomposition (EEMD) is used to select the appropriate intrinsic mode functions (IMFs) through filtering in the respiration band and reconstruct by a linear weighted sum to obtain the photoplethysmography derived respiration (PDR) signal.
Proceedings ArticleDOI

Design of a low power 4×4 multiplier based on five transistor (5-T) half adder, eight transistor (8-T) full adder & two transistor (2-T) AND gate

TL;DR: Simulated results indicate the superior performance of the proposed technique over conventional CMOS multiplier, which achieves a high speed low power design for the multiplier.