This paper presents a state-of-the-art review of error-correcting codes for computer semiconductor memory applications. The construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and for each class of codes the number of check bits required for commonly used data lengths is provided. The implementation aspects of error correction and error detection are also discussed, and certain algorithms useful in extending the error-correcting capability for the correction of soft errors such as α-particle-induced errors are examined in some detail.

Error-correcting codes for semiconductor memory applications: a state-of-the-art review

Error-control coding techniques, implemented by means of self-checking circuits, will improve system reliability.

Error-Correcting Codes and Self-Checking Circuits

The Power4 is an integrated system on a chip (SoC) designed for systems that will initially target enterprise Unix customers and, at a later date, O/S 400 customers. Power4 systems are servers comprised of several Power4 chips. To achieve reliability goals, Power4 system design incorporates fault tolerance throughout the hardware, firmware and operating system. Together, these system components provide concurrent and deferred maintenance, multi-level recovery from errors and run-time diagnostics.

Power4 system design for high reliability

A memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory (30). The assignment of the replacement locations in the alternate memory is made on a selective basis taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code which is used in connection with the memory system. A relatively small writable index, which is addressed by a subset of the main memory address signals, provides a partial address and control fields to the alternate memory in accordance with control data transferred from the host system. Control data is developed by the host system each time it is powered on and is based on identifying each defective location in main memory through a diagnostic routine and analyzing the defect distribution in a way to provide control signals which minimize the number of replacements that are assigned and maximize the number of data words that can be transferred from the memory system to the host system before an uncorrectable error is encountered by the ECC system.

Memory system with selective assignment of spare locations

The POWER4-based p690 systems offer the highest performance of the IBM eServer pSeries™ line of computers. Within the general-purpose UNIX® server market, they also offer the highest levels of concurrent error detection, fault isolation, recovery, and availability. High availability is achieved by minimizing component failure rates through improvements in the base technology, and through design techniques that permit hardand soft-failure detection, recovery, and isolation, repair deferral, and component replacement concurrent with system operation. In this paper, we discuss the faulttolerant design techniques that were used for array, logic, storage, and I/O subsystems for the p690. We also present the diagnostic strategy, fault-isolation, and recovery techniques. New features such as POWER4 synchronous machine-check interrupt, PCI bus error recovery, array dynamic redundancy, and minimum-element dynamic reconfiguration are described. The design process used to verify error detection, fault isolation, and recovery is also described.

Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology

Error correcting codes have been successfully employed to correct errors associated with failures in computer memories. A typical code which has found wide application is the binary Hamming code. This code corrects single bit errors. With the advent of large-scale integration (LSI) storage array technology, the likelihood of errors which exceed the correction and detection capability of such a code is significant. A serious and heretofore unanswered question is the error detection capability of a given code which is implemented and decoded for single error correction, particularly when a storage array chip or card carrying multiple bits from the codeword has failed. In order to identify this capability, a new reliability parameter called package detectability is defined. This paper also presents a method for computing package detectability. The analysis has been performed on a number of codes in order to optimize the packaging for maximum detectability. In addition, a class of distance 3 codes with maximal b-bit package detectability is given.

Bossen

Papers

Measurement and Generation of Error Correcting Codes for Package Failures