The growth of epitaxial semiconductors and oxides has long since revolutionized the electronics and optics fields, and continues to be exploited to uncover new physics stemming from quantum interactions. While the recent emergence of halide perovskites offers exciting new opportunities for a range of thin-film electronics, the principles of epitaxy have yet to be applied to this new class of materials and the full potential of these materials is still not yet known. In this work, single-domain inorganic halide perovskite epitaxy is demonstrated. This is enabled by reactive vapor phase deposition onto single crystal metal halide substrates with congruent ionic interactions. For the archetypical halide perovskite, cesium tin bromide, two epitaxial phases, a cubic phase and tetragonal phase, are uncovered which emerge via stoichiometry control that are both stabilized with vastly differing lattice constants and accommodated via epitaxial rotation. This epitaxial growth is exploited to demonstrate multilayer 2D quantum wells of a halide-perovskite system. This work ultimately unlocks new routes to push halide perovskites to their full potential.

Unlocking the Single‐Domain Epitaxy of Halide Perovskites

Wire resistance in metal wire is one of the factors that degrade the performance of memristor crossbar circuits. In this paper, an analysis of the impact of wire resistance in a memristor crossbar is performed and a compensating circuit is proposed to reduce the impact of wire resistance in a memristor crossbar-based perceptron neural network. The goal of the analysis is to figure out how wire resistance influences the output voltage of a memristor crossbar. It emerges that the wire resistance on horizontal lines causes the neuron's output voltage to vary more than the wire resistance on vertical lines. More interesting, the voltage variation caused by wire resistance on horizontal lines increases proportionally to the length of metal wire. The first column has small voltage variation whereas the last column has large voltage variation. In addition, two adjacent columns have almost the same amount of voltage variation. Under these observations, a memristor crossbar-based perceptron neural network with compensating circuit is proposed. The neuron's outputs of two columns are put into a subtractor circuit to eliminate the voltage variation caused by the wire resistance. The proposed memristor crossbar-based perceptron neural network is trained to recognize the 26 characters. The proposed memristor crossbar shows better recognition rate compared to the previous work when wire resistance is taken into account. The proposed memristor crossbar circuit can maintain the recognition rate as high as 100% when wire resistance is as high as 2.5 Ω. By contrast, the recognition rate of the memristor crossbar without the compensating circuit decreases by 1%, 5%, and 19% when wire resistance is set to be 1.5, 2.0, and 2.5 Ω, respectively.

https://www.mdpi.com/2072-666X/10/10/671/pdf

Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network.

Three-independent-gate FETs (TIGFETs) are Schottky-barrier-based devices, which can be reconfigured to be either n- or p-type allowing for innovative compact logic gate implementations. In this article, we present an aggressively scaled 10-nm gate-all-around silicon–germanium nanowire TIGFET device evaluated with Synopsys Sentaurus Poisson-based Technology Computer-Aided Design (TCAD) simulations at a 0.7-V nominal supply voltage as typically used at this technology node. The operation of the TIGFET device is described in detail, with particular care given to the majority current contributions for each operating mode. When considering a silicon–germanium channel, the maximum TCAD-simulated current drive is 880.20 and $806.58~\mu \text{A}/\mu \text{m}$ for n- and p-type operation, respectively, thus making TIGFET devices competitive with FinFET technology at the 10-nm node. These simulations are verified using device physics calculations. Further simulations of the carrier densities for each of the TIGFET-operating configurations are performed to confirm that the simulated device is operating as intended.

A TCAD Simulation Study of Three-Independent-Gate Field-Effect Transistors at the 10-nm Node

In this paper, we propose a new crossbar architecture of memristors with bipolar inputs for an image recognition application. The performance of the proposed crossbar array with bipolar inputs is based on the simplified Exclusive-NOR function to measure the similarity between the input pattern and the stored patterns. In the proposed architecture, only one crossbar array is used instead of two crossbar arrays. The number of memristors in the proposed architecture is reduced by 50%, when compared to the complementary and the twin architectures. The proposed crossbar architecture with bipolar inputs consumes 16.7% and 7.2% less power than do the complementary and twin architectures. In addition, using only one crossbar array in the proposed architecture can improve the fault tolerance of the crossbar circuit. When 10% of memristors are defective, the proposed crossbar architecture shows a recognition rate improved by 5%, 7% and 4% over that of the memristor binarized neural network, the complementary architecture of the memristor crossbar and the twin architecture of the memristor crossbar when recognizing 10 images.

Single Crossbar Array of Memristors With Bipolar Inputs for Neuromorphic Image Recognition

This paper reports on mobility enhancement in the strained silicon (Si) based field effect transistor (FET) structure corresponds to variation of germanium (Ge) content. The investigations were performed via Silvaco TCAD virtual fabrication and characterizations platforms, ATHENA and ATLAS tools, respectively. In this study, it involved physical modelling of both conventional and strained Si FETs for comparison. The doping dose of the polysilicon was manipulated from 1.0 × 1013 to 4.2 × 1014 cm−2 which results in variation of the channel length from 90 nm to 22 nm. The threshold voltage of both structure had been compared where for the case of the conventional FET, the threshold voltage decreased as the channel length decreased. Accordingly, as the channel length of strained Si FET decreased, the threshold voltage increased with the Ge content in the channel that varied from 10% to 90%. The sub-threshold voltage was observed to increase as the strained Si FET entered the short channel regime, however it continued to slightly decrease as it went deeper into the sub-nanometer technology node. The strained Si FET had up to ∼4.2 times carrier mobility enhancement compared to that of conventional FET as the mole fraction of Ge increased in the Si 1−x Ge x layer of the strain channel. The presence of Ge in the strain layer at the channel has been proved to further enhance the mobility thus improving the drive current. Large drive current aids to the faster switching speed of the transistor, making the circuits to run at higher clock rates.

Effect of Germanium content on mobility enhancement for strained silicon FET

Semiconductor industry is currently facing with the fact that conventional submicron CMOS technology is approaching the end of their capabilities, at least when it comes to scaling the dimensions of the components. Therefore, much attention is paid to device technology that use new technological structures and new channel materials. Modern technological processes, which mainly include ultra high vacuum chemical vapor deposition, molecular beam epitaxy and metal-organic molecular vapor deposition, enable the obtaining of ultrathin, crystallographically almost perfect, strained layers of high purity. In this review paper we analyze the role that such layers have in modern CMOS technologies. It’s given an overview of the characteristics of both strain techniques, global and local, with special emphasis on performance of NMOS biaxial strain and PMOS uniaxial strain. Due to the improved transport properties of strained layers, especially high mobility of charge carriers, the emphasis is on mechanisms to increase the charge mobility of strained silicon and germanium, in light of recent developments in CMOS technology.

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Branko L. Dokić

Papers

Strained Silicon Layer in CMOS Technology