Strained Silicon Layer in CMOS Technology
TLDR
In this article, a review of the characteristics of both strain techniques, global and local, is presented, with special emphasis on performance of NMOS biaxial strain and PMOS uniXial strain.Abstract:
Semiconductor industry is currently facing with the fact that conventional submicron CMOS technology is approaching the end of their capabilities, at least when it comes to scaling the dimensions of the components. Therefore, much attention is paid to device technology that use new technological structures and new channel materials. Modern technological processes, which mainly include ultra high vacuum chemical vapor deposition, molecular beam epitaxy and metal-organic molecular vapor deposition, enable the obtaining of ultrathin, crystallographically almost perfect, strained layers of high purity. In this review paper we analyze the role that such layers have in modern CMOS technologies. It’s given an overview of the characteristics of both strain techniques, global and local, with special emphasis on performance of NMOS biaxial strain and PMOS uniaxial strain. Due to the improved transport properties of strained layers, especially high mobility of charge carriers, the emphasis is on mechanisms to increase the charge mobility of strained silicon and germanium, in light of recent developments in CMOS technology.read more
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References
More filters
Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Journal ArticleDOI
Si/SiGe epitaxial-base transistors. I. Materials, physics, and circuits
David L. Harame,James H. Comfort,John D. Cressler,Emmanuel F. Crabbe,J.Y.-C. Sun,Bernard S. Meyerson,T. Tice +6 more
TL;DR: A detailed review of SiGe epitaxial base technology is presented, which chronicles the progression of research from materials deposition through device and integration demonstrations, culminating in the first SiGe integrated circuit application.
Proceedings ArticleDOI
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell
Scott E. Thompson,Nidhi Anand,Mark Armstrong,C. Auth,B. Arcot,Mohsen Alavi,P. Bai,J. Bielefeld,Robert M. Bigwood,J. Brandenburg,M. Buehler,Stephen M. Cea,V. Chikarmane,C. H. Choi,R. Frankovic,Tahir Ghani,G. Glass,W. Han,Thomas Hoffmann,Makarem A. Hussein,P. Jacob,Ajay Jain,Chia-Hong Jan,Subhash M. Joshi,C. Kenyon,Jason Klaus,S. Klopcic,J. Luce,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,P. Nguyen,H. Pearson,T. Sandford,R. Schweinfurth,R. Shaheed,Swaminathan Sivakumar,M. Taylor,B. Tufts,Charles H. Wallace,P.-H. Wang,Cory E. Weber,Mark T. Bohr +43 more
TL;DR: In this paper, a leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented.
Proceedings ArticleDOI
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
Kern Rim,Jack O. Chu,Huajie Chen,Keith A. Jenkins,Thomas S. Kanarsky,Kam-Leung Lee,Anda Mocuta,Huilong Zhu,Ronnen Andrew Roy,J. Newbury,John A. Ott,K. Petrarca,Patricia M. Mooney,D. Lacey,Steven J. Koester,Kevin K. Chan,Diane C. Boyd,Meikei Ieong,Hon-Sum Philip Wong +18 more
TL;DR: In this article, current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFets with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/ sub eff/ below 80 nm and 60 nm.