A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds.

Adaptive Estimation of Memory Cell Read Thresholds

A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

Reading memory cells using multiple thresholds

The disclosure provides systems and methods of use of an HVAC graphical interface dashboard. In various embodiments the dashboard includes a weather tab, wherein invoking the weather tab advances to a weather screen. The dashboard also includes an indoor humidity tab, wherein invoking the indoor humidity tab advances to a humidity screen which displays at least a current indoor humidity, wherein the humidity screen interprets a percentage of humidity for a user. A programs tab and a home tab are also provided. A button of the dashboard turns a color, such as an inverse color, when it is touched.

System and method of use for a user interface dashboard of a heating, ventilation and air conditioning network

A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

Distortion estimation and cancellation in memory devices

A method for storing data in a memory (28) that includes analog memory cells (32) includes identifying one or more defective memory cells in a group of the analog memory cells. An Error Correction Code (ECC) is selected responsively to a characteristic of the identified defective memory cells. The data is encoded using the selected ECC and the encoded data is stored in the group of the analog memory cells. In an alternative method, an identification of one or more defective memory cells among the analog memory cells is generated. Analog values are read from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells. The analog values are processed using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data.

Automatic defect management in memory devices

A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested.

In Situ Verification of Capacitive Power Support

To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I 2 C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.

Verifying data integrity of a non-volatile memory system during data caching process

A mechanism detects cable length in a storage subsystem with wide ports. The mechanism uses in-situ bidirectional cable wrapping for determining different cable lengths. The mechanism under-margins transmitter output to failure for each external port and even for each PHY within a wide port. Based on the transition point from “good” wrap to “bad” wrap, the cable length may be determined. The transition point identifies if the cable is long or short, at which point the optimum tuning parameters can accordingly be set. A calibration mechanism calibrates the high speed transmitter/receiver pair characteristics, and, thus, optimizes the transmission performance between subsystems. The calibration mechanism mitigates the need for frequent error correction and does not incur the performance degradation associated with error correction techniques.

Method and Procedure for Detecting Cable Length in a Storage Subsystem with Wide Ports

A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array The flash array includes a first flash port and a second flash port The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port The first SSDC and the second SSDC are both configured to connect to all memory within the flash array and the first SSDC, second SSDC, and flash array are within a common solid state drive

Method Apparatus and System for a Redundant and Fault Tolerant Solid State Disk

A data processing unit including a first active cooling device configured to respond to a first control signal and a second active cooling device configured to respond to a second control signal. The control signals may be any type of control signal suitable to control the operation of the first and second active cooling devices. The data processing unit also includes a first control function selectively capable of providing the first control signal and/or the second control signal, and a second control function selectively capable of providing the first control signal and/or the second control signal. Logic associated with the first and second control functions is included to determine which of the control functions will provide which control signal at a specific time. Logic and/or switching or isolation apparatus is also included to prevent both the first and second control functions from attempting to provide one of the control signals simultaneously.

Brian James Cagno

Papers

In Situ Verification of Capacitive Power Support

Verifying data integrity of a non-volatile memory system during data caching process

Method and Procedure for Detecting Cable Length in a Storage Subsystem with Wide Ports

Method Apparatus and System for a Redundant and Fault Tolerant Solid State Disk

Cooling system control with clustered management services