The invention regards an method for estimating the end of lifetime for a power semiconductor device, such as an IGBT power module, comprising the steps of; establishing the temperature of the power semiconductor device, determining the voltage drop over the power semiconductor device for at least one predetermined current where the current is applied when the power semiconductor device is not in operation, wherein the end of lifetime is established dependent on the change in a plurality of determined voltage drops.

Method for estimating the end of lifetime for a power semiconductor device

The invention relates to an IGBT (insulated gate bipolar transistor) dynamic performance test device, which comprises a test current generating circuit, a first temperature collection and storage system, a second temperature collection and storage system, an oscilloscope, an IGBT driving circuit and an IGBT over-temperature protection system, wherein the IGBT over-temperature protection system is connected with the IGBT driving circuit, the test current generating circuit, the first temperature collection and storage system, the second temperature collection and storage system and the oscilloscope are respectively independent, and during testing, an IGBT test module is respectively connected with the test current generating circuit, the first temperature collection and storage system, the second temperature collection and storage system, the oscilloscope, the IGBT driving circuit and the IGBT over-temperature protection system. The IGBT dynamic performance test device has the advantages that the accumulated heat of an internal heating chip and the heat of a copper base board of an IGBT module can be simultaneously and automatically collected, further, the heat resistance parameters of the module can be extracted, and the work frequency of the IGBT module can be adjusted in real time.

IGBT (insulated gate bipolar transistor) dynamic performance test device and operation method of IGBT dynamic performance test device

The invention relates to a temperature conversion method and a low-power high-precision integrated temperature sensor. The low-power high-precision integrated temperature sensor is composed of a band gap reference circuit with a sensing core, a positive and negative synchronous switch capacitor integral circuit, a current source and a sampling capacitor dynamic element matching module, a clock generating circuit, a divider and buffer circuit and a fully differential analog-to-digital converter. The sensing core circuit in the traditional technology and the band gap reference circuit are combined and integrated, so that the circuit structure is simplified; the current source dynamic element matching module is arranged and thus a base-emitter junction voltage difference in proportion to the absolute temperature is generated, wherein the polarity of the voltage difference changes alternately; with the novel positive and negative synchronous switch capacitor integral circuit, the improved temperature conversion function is completed and the dynamic range utilization rate of the analog-to-digital converter is improved; dynamic element matching is carried out on the sampling capacitor, thereby improving the integral accuracy; and the analog-to-digital converter is used for carrying out quantization processing on an effective temperature signal to provide a digital output. Therefore, the temperature error and circuit power consumption of the sensor can be effectively reduced; and the method and the sensor are suitable for the low-power high-precision temperature sensing application.

Temperature conversion method and a low-power high-precision integrated temperature sensor

Monitoring aging in an electric drive system includes energizing the electric drive system such that electrical current flows through a power semiconductor device therein, determining a value indicative of a voltage across the power semiconductor device, at a current level where voltage is substantially independent of temperature, comparing the determined value with a reference value, and outputting a signal responsive to a difference between the values that is indicative of an aging state of the power semiconductor device.

Aging determination of power semiconductor device in electric drive system

Estimating junction temperature in a power semiconductor includes monitoring electrical current direction so as to determine which of a first and a second power semiconductor is in an on-state, and sensing a voltage drop across the one of the power semiconductors. Voltage drop may be correlated with temperature according to a gain dependent upon a level of the electrical current.

Temperature estimation in power semiconductor device in electric drive system

The disclosure relates to an electronic control circuit for an electric device, in particular designed as a commutation electric system of an EC motor, having a plurality of power transistors which are controlled in an operating mode for controlling the device. An additional, similar, non-charged reference transistor in the operating mode of the power transistors is arranged or formed together with the power transistors on a common support or substrate. The circuit also comprises means for applying to the reference transistor and at least one power transistor, respectively one test flow in a test mode for measuring the respective associated saturation voltage and for evaluating saturation tension differences resulting from the measured saturation voltages of the reference transistors and the respective power transistors taking into account the temperature of the support/substrate produced during the measurement as the criterion for an aging process and an expected remaining service life of the power transistors. The disclosure also relates to a method for monitoring power transistors in said type of electronic control circuit with respect to the expected remaining service life thereof.

Electronic control circuit comprising power transistors and method for monitoring the service life of the power transistors

A master-slave system includes a master unit having a digital output for providing a signal or a serial signal sequence of signals, and at least two slave units. Each of the slave units includes at least one digital serial memory having a size of one bit, and each slave unit includes an input and an output. The slave units are serially connected to one another via the inputs and the outputs via a signal line ( 5 ). The output of a first slave unit is connected via the signal line to the digital output of the master unit. The master slave system is configured so that a signal supplied by the digital output is detected at the input of the slave unit, in order to raise the address of the corresponding slave unit in each case by the value “1”, to store the signal change in the memory and to output a signal corresponding to the content of the memory at the output of the memory.

Dynamically addressable master slave system and method for dynamic addressing of slave units

The invention relates to a dynamically addressable master-slave system and a method for dynamically addressing slave units, wherein a master unit (1) and a plurality of slave units (2) are provided and the slave units (2) and the master unit (1) are connected to one another via a bus system (3). At least one broadcast command (B) is received by the master unit (1) via a bus line (3a) of the bus system (3), wherein the master-slave system (100) is configured such that the master unit (1) can be activated on the one hand On the other hand, the corresponding broadcast command (B) can be sent to the slave units (2) in order to perform a dynamic address process for the slave address (A1, ..., Ai, ..., An), wherein the slave units (2) have an address input end (2a) and an address output end (2b), respectively, and are serially connected to each other by an address device (4) separated from the bus line (3a).

Wireless allocation of network addresses

Die vorliegende Erfindung Master-Slave-System (100) umfassend eine Master-Einheit (1) mit einem Digitalausgang (6) zur Bereitstellung eines Signals oder eine serielle Signalfolge von Signalen und wenigstens zwei Slave-Einheiten (2), wobei die Slave-Einheiten (2) jeweils einen digitalen seriellen Speicher (3) mit einer Grose von einem Bit aufweisen und jeweils einen Eingang (3a) und einen Ausgang (3b) aufweisen, wobei die Slave-Einheiten (2) uber die Eingange (3a) und die Ausgange (3b) uber eine Signalleitung (5) seriell miteinander verbunden sind und wobei der Eingang (3a) einer ersten Slave-Einheit (2) uber die Signalleitung (5) mit dem Digitalausgang (6) der Master-Einheit (1) verbunden ist, wobei das Master-Slave-System (100) so konfiguriert ist, dass am Eingang (3a) der Slave-Einheit (2) ein vom Digitalausgang (6) bereitgestelltes Signal (Signalwechsel) detektiert wird, um die Adresse (A) der entsprechenden Slave-Einheit (2) jeweils um den Wert „1” zu erhohen, den Signalwechsel im Speicher (3) zu hinterlegen und ein zum Inhalt des Speichers (3) korrespondierendes Signal am Ausgang (3b) des Speichers (3) auszugeben.

Dynamisch adressierbares master-slave-system sowie verfahren zum dynamischen adressieren von slave-einheiten

Die Erfindung betrifft den Betrieb sowie eine Schaltungsanordnung (1) fur einen im Hinblick auf die Eingangsspannung veranderbaren Netzanschluss (1-phasig/3-phasig), die mit einem Mittelabgriff (M) zwischen den Kondensatoren (C) uber eine Verbindungsleitung (10) mit einem Neutralleiter (N) einer Eingangs-Wechselspannungsquelle verbunden ist.

Bürkert Martin

Papers

Electronic control circuit comprising power transistors and method for monitoring the service life of the power transistors

Dynamically addressable master slave system and method for dynamic addressing of slave units

Wireless allocation of network addresses

Dynamisch adressierbares master-slave-system sowie verfahren zum dynamischen adressieren von slave-einheiten

Vorrichtung zur effizienten netzartunabhängigen Zwischenkreisaufbereitung