We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem. We have implemented this strategy in a pair of tools called ASTRX and OBLX. To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTRX/OBLX has resynthesized circuits in an afternoon that, for some prior approaches, had required months. To show the viability of the approach on difficult circuits, we have resynthesized a recently published (and patented), high-performance operational amplifier; ASTRX/OBLX achieved performance comparable to the expert manual design. And finally, to test the limits of the approach on industrial-sized problems, we have synthesized the component cells of a pipelined A/D converter; ASTRX/OBLX successfully generated cells 2-3/spl times/ more complex than those published previously.

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Synthesis of high-performance analog circuits in ASTRX/OBLX

Together with the increase in electronic circuit complexity, the design and optimization processes have to be automated with high accuracy. Predicting and improving the design quality in terms of performance, robustness and cost is the central concern of electronic design automation. Generally, optimization is a very difficult and time consuming task including many conflicting criteria and a wide range of design parameters. Particle swarm optimization (PSO) was introduced as an efficient method for exploring the search space and handling constrained optimization problems. In this work, PSO has been utilized for accommodating required functionalities and performance specifications considering optimal sizing of analog integrated circuits with high optimization ability in short computational time. PSO based design results are verified with SPICE simulations and compared to previous studies.

Analog circuit sizing via swarm intelligence

An 8-MHz seventh-degree elliptic-function low-pass filter is described, demonstrating an approach to low-distortion antialias filtering for high-definition video applications. The filter's performance goals are achieved through the use of circuit design principles that capitalize on the strengths of BiCMOS technology. The integrator circuits composing the filter consist of a new wideband low-distortion transconductor circuit and a unique BiCMOS Miller-stage circuit. Integrator time constants are determined by stable RC products, enabling a simplified filter calibration scheme that is insensitive to temperature-induced variations and requires no phaselock circuits. The prototype filter IC, consisting of seven integrators assembled in an active-ladder configuration, was fabricated in a 10-V, 2- mu m 2.5-GHz BiCMOS technology that also features thin-film resistors and polysilicon-plate capacitors. Measured results from the calibrated filter show passband flatness of 0.2 dB, with aberrations of less than +or-1 dB over a 100 degrees C temperature range. Stopband attenuation meets its designed goal of 60 dB. Driven by 7-V/sub pp/, differential input signals, the filter exhibits less than -72-dBc third-order intermodulation distortion products at 1 MHz. For 5-V/sub pp/ inputs at 4 MHz, third-order intermodulation spurs remain below -65 dBc. >

A BiCMOS low-distortion 8-MHz low-pass filter

This paper introduces an automated circuit design system for the evolution and subsequent invention of CMOS amplifiers. The proposed system relies on a mix of genetic programming and a new topology-independent design optimization method referred to as current-flow analysis. Genetic programming evolves new circuit topologies from the collection of primitive devices and basic building blocks. Current-flow analysis screens and corrects circuits using topology-independent design rules. Experimental results show a promising improvement on the design of operational amplifiers that make the automated analog design environment using genetic programming a lot more practical.

The invention of CMOS amplifiers using genetic programming and current-flow analysis

A current-mode approach, involving current conveyor and current-mode amplifiers, is playing an increasingly important role in the development of many new high-performance circuits for signal processing applications. This paper will review the recent trends that have emerged over the last two years in certain areas of current-mode design, with particular attention to current conveyors and amplifiers.

Tutorial review Trends in current conveyor and current-mode amplifier design

A methodology called ISAID for the automated generation of analog integrated circuit designs is presented. The methodology makes use of a hierarchical design procedure to break down the required system specifications into transistor descriptions. The methodology provides a correction procedure which enables designs which fail to meet the required specifications when simulated or laid out to be corrected either by altering circuit component sizes or by making changes in the designed topology itself. Some approaches to analog IC design are briefly reviewed. A two-stage operational amplifier design example is presented. >

ISAID-a methodology for automated analog IC design

Some basic ideas are presented for the application of current-mode circuits as compensation networks to reduce integrator errors for filter applications. A current-conveyor compensation network is introduced which theoretically results in significant improvements in the gain and phase errors of an integrator. It is shown that the main requirement is for the current conveyor to have a high gain-bandwidth product, and circuits which achieve this are presented. The application of the proposed compensation to integrated continuous-time and switched-capacitor integrators is briefly discussed, and key performance improvements are identified. >

High frequency, precision integrators using current-conveyor compensation techniques

An active compensation technique for two-stage CMOS operational amplifiers is described. The settling response of a two-stage operational amplifier is critically dependent upon an effective capacitance. The introduction of a current follower to the commonly employed voltage follower and capacitor compensation network significantly reduces this capacitance, resulting in a considerable reduction in operational amplifier setting time. Simulated performances using ideal followers indicate ultimate dynamic performance improvements. >

Improved operational amplifier settling behaviour using active compensation techniques

The prospect of fully automated analogue circuit design by a system whose input is a performance specification and whose output is a mask set, has attracted the attention of researchers for many years, and a few developmental systems are already in existence. The aim of this paper is to describe, necessarily in outline, the CHIPAIDE system currently being developed at Imperial College. Like some other systems, CHIPAIDE contains a knowledge-based circuit generation module and a layout generation module. However, if differs from other systems in the algorithmic bases of these modules, in the inclusion of optimisation and tolerance design modules and, principally, in the close interaction that occurs between the four modules which comprise the CHIPAIDE system. Each module is separately described.

https://ieeexplore.ieee.org/iel3/1866/4818/00190115.pdf

CHIPAIDE: a new approach to analogue integrated circuit design

In order to meet future integration trends where full analogue and digital systems will be incorporated onto a single integrated circuit, automated analogue synthesis tools will be required. The systems surveyed in this paper address this need with differing approach and versatility. The systems considered are: IDAC/ILAC which are products of CSEM in Switzerland, OASYS/ANAGRAM from Carnegie Mellon University and OPASYN developed by the University of California, Berkeley. OASYS and IDAC are capable of synthesising several different analogue functions with moderate specifications while OPASYN is specifically designed for op-amp synthesis where a numerical optimizer is used to achieve more stringent requirements. In all cases the systems accept high level specifications and produce a set of process-specific fabrication masks. In view of the anticipated importance of analogue synthesis tools, considerable research is being undertaken to extend their capability to higher performance analogue circuits. In addition, other factors such as the number of analogue circuit functions that can be synthesised and the circuit design time need to be improved.

https://ieeexplore.ieee.org/iel3/2013/5106/00198317.pdf

C.A. Makris

Papers

ISAID-a methodology for automated analog IC design

High frequency, precision integrators using current-conveyor compensation techniques

Improved operational amplifier settling behaviour using active compensation techniques

CHIPAIDE: a new approach to analogue integrated circuit design

Approaches to analogue IC synthesis