Blind identification of source signals is studied from both theoretical and algorithmic aspects. A mathematical structure is formulated from which the acceptable indeterminacy is represented by an equivalence relation. The concept of identifiability is then defined. Two identifiable cases are shown along with blind identification algorithms. The performance of FOBI (fourth-order blind identification), EFOBI (extended FOBI), and AMUSE algorithms is evaluated by some heuristic arguments and simulation results. It is shown that EFOBI outperforms the FOBI algorithm, and the AMUSE algorithm performs better than EFOBI in the case of nonwhite source signals. AMUSE is applied to a speech extraction problem and shown to have promising results. >

Indeterminacy and identifiability of blind identification

Blind source separation consists of recovering a set of signals of which only instantaneous linear mixtures are observed. Thus far, this problem has been solved using statistical information available on the source signals. This paper introduces a new blind source separation approach exploiting the difference in the time-frequency (t-f) signatures of the sources to be separated. The approach is based on the diagonalization of a combined set of "spatial t-f distributions". In contrast to existing techniques, the proposed approach allows the separation of Gaussian sources with identical spectral shape but with different t-f localization properties. The effects of spreading the noise power while localizing the source energy in the t-f domain amounts to increasing the robustness of the proposed approach with respect to noise and, hence, improved performance. Asymptotic performance analysis and numerical simulations are provided.

Blind source separation based on time-frequency signal representations

We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem. We have implemented this strategy in a pair of tools called ASTRX and OBLX. To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTRX/OBLX has resynthesized circuits in an afternoon that, for some prior approaches, had required months. To show the viability of the approach on difficult circuits, we have resynthesized a recently published (and patented), high-performance operational amplifier; ASTRX/OBLX achieved performance comparable to the expert manual design. And finally, to test the limits of the approach on industrial-sized problems, we have synthesized the component cells of a pipelined A/D converter; ASTRX/OBLX successfully generated cells 2-3/spl times/ more complex than those published previously.

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Synthesis of high-performance analog circuits in ASTRX/OBLX

Together with the increase in electronic circuit complexity, the design and optimization processes have to be automated with high accuracy. Predicting and improving the design quality in terms of performance, robustness and cost is the central concern of electronic design automation. Generally, optimization is a very difficult and time consuming task including many conflicting criteria and a wide range of design parameters. Particle swarm optimization (PSO) was introduced as an efficient method for exploring the search space and handling constrained optimization problems. In this work, PSO has been utilized for accommodating required functionalities and performance specifications considering optimal sizing of analog integrated circuits with high optimization ability in short computational time. PSO based design results are verified with SPICE simulations and compared to previous studies.

Analog circuit sizing via swarm intelligence

This paper introduces an automated circuit design system for the evolution and subsequent invention of CMOS amplifiers. The proposed system relies on a mix of genetic programming and a new topology-independent design optimization method referred to as current-flow analysis. Genetic programming evolves new circuit topologies from the collection of primitive devices and basic building blocks. Current-flow analysis screens and corrects circuits using topology-independent design rules. Experimental results show a promising improvement on the design of operational amplifiers that make the automated analog design environment using genetic programming a lot more practical.

The invention of CMOS amplifiers using genetic programming and current-flow analysis

A methodology called ISAID for the automated generation of analog integrated circuit designs is presented. The methodology makes use of a hierarchical design procedure to break down the required system specifications into transistor descriptions. The methodology provides a correction procedure which enables designs which fail to meet the required specifications when simulated or laid out to be corrected either by altering circuit component sizes or by making changes in the designed topology itself. Some approaches to analog IC design are briefly reviewed. A two-stage operational amplifier design example is presented. >

ISAID-a methodology for automated analog IC design

A method of estimating the parametric yield of a MOSFET integrated circuit using a piecewise-linear approximation to the yield body is presented. First results show that the method is useful in estimating yield as well as predicting the performance of both analog and digital MOSFET circuits. The statistical changes that are considered are the geometrical ones (as they are often the most important), together with the oxide capacitance and the flat band voltage, which have been proven to fully describe the variation in behavior of MOSFET circuits; the other parameters have a smaller influence and have been neglected for simplicity. >

Parametric yield estimation for a MOSFET integrated circuit

The prospect of fully automated analogue circuit design by a system whose input is a performance specification and whose output is a mask set, has attracted the attention of researchers for many years, and a few developmental systems are already in existence. The aim of this paper is to describe, necessarily in outline, the CHIPAIDE system currently being developed at Imperial College. Like some other systems, CHIPAIDE contains a knowledge-based circuit generation module and a layout generation module. However, if differs from other systems in the algorithmic bases of these modules, in the inclusion of optimisation and tolerance design modules and, principally, in the close interaction that occurs between the four modules which comprise the CHIPAIDE system. Each module is separately described.

https://ieeexplore.ieee.org/iel3/1866/4818/00190115.pdf

CHIPAIDE: a new approach to analogue integrated circuit design

In order to meet future integration trends where full analogue and digital systems will be incorporated onto a single integrated circuit, automated analogue synthesis tools will be required. The systems surveyed in this paper address this need with differing approach and versatility. The systems considered are: IDAC/ILAC which are products of CSEM in Switzerland, OASYS/ANAGRAM from Carnegie Mellon University and OPASYN developed by the University of California, Berkeley. OASYS and IDAC are capable of synthesising several different analogue functions with moderate specifications while OPASYN is specifically designed for op-amp synthesis where a numerical optimizer is used to achieve more stringent requirements. In all cases the systems accept high level specifications and produce a set of process-specific fabrication masks. In view of the anticipated importance of analogue synthesis tools, considerable research is being undertaken to extend their capability to higher performance analogue circuits. In addition, other factors such as the number of analogue circuit functions that can be synthesised and the circuit design time need to be improved.

https://ieeexplore.ieee.org/iel3/2013/5106/00198317.pdf

Approaches to analogue IC synthesis

A number of researchers have directed their efforts to expert system methods in order to automate the analogue design process. Generally, these systems combine algorithmic and heuristic knowledge together with design procedures of expert circuit designers to aid the generation of sized transistor level circuits from performance specifications. In this paper the authors first review some existing approaches and then introduce a new approach which overcomes several of their drawbacks. To provide a suitable benchmark for the comparison of these approaches they first describe the familiar analogue circuit design process. So far, only operational amplifiers have been considered.

http://ieeexplore.ieee.org/iel3/1156/1868/00051695.pdf

C.M. Berrah

Papers

ISAID-a methodology for automated analog IC design

Parametric yield estimation for a MOSFET integrated circuit

CHIPAIDE: a new approach to analogue integrated circuit design

Approaches to analogue IC synthesis

A methodology for automated generation of analogue integrated circuits