Electromigration is an important concern in very large scale integrated circuits. In narrow, confined metal interconnects used at the chip level, the electromigration flux is resisted by the evolution of mechanical stresses in the interconnects. Solutions for the differential equation governing the evolution of back stresses are presented for several representative cases, and the solutions are discussed in the light of experimental as well as theoretical developments from the literature.

Stress evolution due to electromigration in confined metal lines

Stress-induced voiding is observed in Cu-based, deep-submicron, dual-damascene technologies where voids are formed under the via when the via connects to a wide metal lead below it. The voiding results from the supersaturation of vacancies that develops due to grain growth when the Cu is not properly annealed prior to being fully constrained. The driving force for voiding is shown to be stress migration with a maximum in voiding rate observed at /spl sim/190/spl deg/C. A diffusional model is presented which shows that the voiding mechanism is an issue primarily for vias connected to wide Cu leads. A thermomechanical stress exponent of 3.2 and a diffusional activation energy of 0.74 eV were determined for this stress-induced voiding mechanism.

Stress-induced voiding under vias connected to wide Cu metal leads

Microelectronic circuits often fail because cracks and voids cause open circuits in their interconnects. Many of the mechanisms of failure are believed to be associated with diffusion of material along the surfaces, interfaces or grain boundaries in the line; material may also flow through the lattice of the crystal. The diffusion is driven by variations in elastic strain energy and stress in the solid, and by the flow of electric current. To predict the conditions necessary for failure to occur in an interconnect, one must account for the influence of both deformation and electric current flow through the interior of the solid, and also for the effects of mass flow. To this end, we describe a two dimensional finite element method for computing the motion and evolution of voids by surface diffusion in an elastic, electrically conducting solid. Various case studies are presented to demonstrate the accuracy and capabilities of the method, including the evolution of a void towards a circular shape due to diffusion driven by surface energy, the migration and evolution of a void in a conducting strip due to electromigration induced surface diffusion, and the evolution of a void in an elastic solid due to strain energy driven surface diffusion.

A finite element analysis of the motion and evolution of voids due to strain and electromigration induced surface diffusion

We report a diffuse interface or phase field model for simulating electromigration and stress-induced void evolution in interconnect lines. Our approach is based on the introduction of an order parameter field to characterize the damaged state of the interconnect. The order parameter takes on distinct uniform values within the material and the void, varying rapidly from one to the other over narrow interfacial layers associated with the void surface. The evolution of this order parameter is shown to be governed by a form of the Cahn–Hilliard equation. An asymptotic analysis of the equation demonstrates, as intended, that the zero contour of the order parameter tracks the motion of a void evolving by diffusion under the coupled effects of stresses and the “electron wind” force. An implicit finite element scheme is used to solve the modified Cahn–Hilliard equation, together with equations associated with the accompanying mechanical and electrical problems. The diffuse interface model is applied to simulate a range of problems involving void evolution in interconnect lines. Results obtained are shown to be in excellent agreement with those computed previously using equivalent sharp interface models.

Diffuse interface model for electromigration and stress voiding

Copper deposition and thermal stability issues in copper-based metallization for ULSI technology

Thermal stress‐induced voiding in narrow aluminum‐based metallizations used as interconnects in microelectronic circuits has recently become a serious reliability concern. Room‐temperature stress relaxation and associated physical phenomena in passivated and unpassivated aluminum‐based metallizations, subsequent to exposure to high temperatures, are analyzed based both on theoretically estimated and experimentally determined thermal stresses. It is shown that stress relaxation at longer times involves mainly dislocation climb, while short‐term relaxation during cool down from higher temperatures, and immediately thereafter, involves significant dislocation glide. Void growth, frequently observed in passivated metallizations, provides a new source of atoms to feed stress relaxation by the same processes as in the absence of voiding.

C. A. Paszkiet

Papers

Mechanisms of thermal stress relaxation and stress‐induced voiding in narrow aluminum‐based metallizations