IEEE International Solid-State Circuits Conference

A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

High-voltage transistor with multi-layer conduction region

This paper examines error control coding (ECC) use in wireless sensor networks (WSNs) to determine the energy efficiency of specific ECC implementations in WSNs. ECC provides coding gain, resulting in transmitter energy savings, at the cost of added decoder power consumption. This paper derives an expression for the critical distance dCR, the distance at which the decoder's energy consumption per bit equals the transmit energy savings per bit due to coding gain, compared to an uncoded system. Results for several decoder implementations, both analog and digital, are presented for dCR in different environments over a wide frequency range. In free space, dCR is very large at lower frequencies, suitable only for widely spaced outdoor sensors. In crowded environments and office buildings, dCR drops significantly, to 3 m or greater at 10 GHz. Interference is not considered; it would lower dCR. Analog decoders areshown to be the mostenergy-efficient decoders in this study.

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Error control coding in low-power wireless sensor networks: when is ECC energy-efficient?

A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

High-voltage lateral transistor with a multi-layered extended drain structure

A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain (19) with an extended well region (17) having one or more buried layers (18) of opposite conduction type sandwiched therein. The one or more buried layers (18) create an associated plurality of parallel JFET conduction channels (25) in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.

Method of making a high-voltage transistor with multiple lateral conduction layers

A semiconducting device and method of making the same are provided. The semiconducting device is provided with a gate, a source and a drain disposed on one side of a current carrying layer and a substrate formed from one type of semiconducting material disposed on the other side thereof. The current carrying layer includes a bulk region formed from said one type of semiconducting material and a drift region formed from the opposite type of semiconducting material, the bulk and the drift regions of which form a pn junction. The drift region includes a pair of parallel passages, one passage of which has a lower doping concentration than the other. The bulk region includes a first and a second portion, the first portion of which isolates the second portion from the other passage and has a lower doping concentration than the second portion and the one passage. The one passage is also extended so as to isolate the bulk region from the substrate. Source and drain regions located on opposite sides of the junction are also provided and formed from the opposite type of semiconducting material. The source and drain regions are doped to have a higher doping concentration than the other passage. Thus, the semiconducting device maintains a relatively high breakdown voltage whilst exhibiting a low on-resistance.

Semiconductor LDMOS device with upper and lower passages

The J - V characteristics of Schottky barrier diodes with long drift regions are discussed in this paper. A simple physical model describing conductivity modulation effects under high level injection is derived. Solution for the electron and hole carrier profile, current densities, electric field, voltage drop and the amount of stored charge as a function of the total current density is presented. An empirical model which spans low and high injection levels is also proposed. The model uses the traditional formula for low injection condition and switches gradually to the high level injection model derived here when the amount of minority carrier injection becomes appreciable. The validity of the complete model is verified by comparison with simulated and experimental results.

Schottky barrier diode characteristics under high level injection

This paper describes the implementation of an asynchronous 64-state, 1/2-rate Viterbi decoder using an original architecture and design methodology. The decoder is intended for wireless communications applications, where bit rates over 100 Mb/s and minimum power consumption are sought. The choice of an asynchronous design was predicated by the power and speed advantages of such a methodology. Asynchronous designs are inherently data driven and are active only when doing useful work, enabling considerable savings in power and operating at the average speed of all components. The decoder, implemented in a 0.18 /spl mu/m CMOS technology, occupies an area of 2 mm/sup 2/ and operates above 200 Mb/s while consuming 85 mW: a 55% power reduction when compared to state of the art synchronous design implemented in a 0.25 /spl mu/m technology.

Low-power asynchronous viterbi decoder for wireless applications

This paper discusses the design and characterization of a track-and-hold amplifier (THA) and a comparator which are the essential building blocks of an 8bit, 12.5GS/s folding-interpolating analog to digital converter (ADC) with a 3GHz bandwidth. The circuits are implemented in a 0.25µm, 190GHz SiGe BiCMOS process. The THA occupies an area of 0.5mm2. It features a SNDR of 47dB or 7.5bits ENOB for a 3GHz bandwidth, a hold time of 21ps with a droop rate of 11mV/80ps and a power dissipation of 230mW from a 3.3V supply. The comparator occupies an area of 0.38mm2 and exhibits an input sensitivity of ±2mV, an input offset voltage of 1.5mV, latch and recovery times of 19 and 21ps respectively and a power dissipation of 150mW from a 3.3V supply.

Track-and-hold and comparator for a 12.5GS/s, 8bit ADC

A simple CAD model for the I/V characteristics of long-channel depletion-mode MOSFETs is presented. The model is applicable to both shallow and deep channel devices and provides a complete set of characterisation equations for eachmode of operation. The model also enhances qualitative understanding of the device behaviour and provides direct correlation between the electrical characteristics and the physical, technological and geometrical design parameters of the MOSFETs. Good agreement between the simplified model and measured device characteristics justifies its validity.

C. Andre T. Salama

Papers

Semiconductor LDMOS device with upper and lower passages

Schottky barrier diode characteristics under high level injection

Low-power asynchronous viterbi decoder for wireless applications

Track-and-hold and comparator for a 12.5GS/s, 8bit ADC

Depletion mode MOSFET modelling for CAD