The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD's) into back end interconnect architectures have made integrating copper bumps challenging, i.e. low-k ILD cracking that often leads to partial or complete die failure. For the 65nm technology node, Intel has successfully incorporated copper die-side bumps mated to eutectic tin-lead (SnPb) package-side bumps in high volume manufacturing (HVM). Advantages of using copper die bumps include lowering the bump critical dimension (CD) floor, continued downward scaling of passivation opening size, a drastically simplified underbump metallization (UBM) scheme that projects to improved electromigration resistance, and extensions to higher 10 densities. This paper will discuss some of these gains.

Copper die bumps (first level interconnect) and low-K dielectrics in 65nm high volume manufacturing

An interfacial-fracture-mechanics-based simulation methodology has been developed to study the flip-chip packaging effect on the copper/low-k structures. Multilevel submodeling techniques have been used to bridge the scale difference between the flip-chip packages and the metal/dielectric stacks. To achieve a smaller feature size and higher speed in future chips, SiO/sub 2/ can be replaced with low-k dielectric material in all via and trench layers or the number of metal layers can be increased. The effect of both packaging options has been evaluated. With either option, the future flip-chip copper/low-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provides a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flip-chip packages.

Analysis of flip-chip packaging challenges on copper/low-k interconnects

Die singulation, also known as wafer dicing, is reviewed in terms of the brief history, critical challenges, characterization of singulation quality, different singulation technologies and underlying mechanisms, and post-singulation die strength enhancement. Mechanical blade dicing has been the workhorse of die separation in the semiconductor manufacturing process. It faces growing challenges due to the adoption of copper/low-k dielectric interconnect structures, thin and ultra-thin wafers, die attach films, narrow dicing streets, and complex stacked structures on the dicing streets. Key dicing quality characteristics are chipping, delamination, kerf geometry, die side wall damage, die surface contamination, and die strength degradation. Various die singulation technologies have been developed to address these challenges and quality issues, including dicing by thinning, laser based approaches, laser and mechanical hybrid method, and plasma dicing. Die strength is a critical parameter for thin and ultra-th...

Die singulation technologies for advanced packaging: A critical review

A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads

We explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130-nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing pose serious challenges to the implementation of such materials in high-volume manufacturing. We consider the cases of two ILD materials, carbon-doped silicon dioxide and low-k spin-on-polymer, to illustrate the impact of the ILD choice on the process technology and reliability of copper interconnects.

Materials' impact on interconnect process technology and reliability

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.

C. Goldberg

Papers

Impact of flip-chip packaging on copper/low-k structures