Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire/spl acute/ interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.

Packaging effects on reliability of Cu/low-k interconnects

The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD's) into back end interconnect architectures have made integrating copper bumps challenging, i.e. low-k ILD cracking that often leads to partial or complete die failure. For the 65nm technology node, Intel has successfully incorporated copper die-side bumps mated to eutectic tin-lead (SnPb) package-side bumps in high volume manufacturing (HVM). Advantages of using copper die bumps include lowering the bump critical dimension (CD) floor, continued downward scaling of passivation opening size, a drastically simplified underbump metallization (UBM) scheme that projects to improved electromigration resistance, and extensions to higher 10 densities. This paper will discuss some of these gains.

Copper die bumps (first level interconnect) and low-K dielectrics in 65nm high volume manufacturing

MEMS switches provide high isolation when open and low insertion loss vhen closed. They also Iuve the advantages of low powr consumption. Thcrefore, RF MEMS switches are an attractive solution to switch antenna bands and transmit/rcceive switching for future multi-band. high bandwidth cell phones. However: Stiction is a major concern for resistive sn-itchcs with metal-to-mctal contact. An iterative-coupled electrostatic-structuml analysis is utilized to evaluate the effect of design parameters on restoring force of MEMS switches. Parameters including mctal thickness, diclcctric thickness. beam-to-ground gap height: metal and dielectric width. and cantilcvcr beam length can be evaluated. The clcctrostatic force is first calculated based on the clcctrical field component. A strnctural analysis is then performed to determine the cantilever beam deflection due to the electrostatic force. A unique integrated empiricalnumerical method is used to qualitativel?- dctcrminc the stiction force bascd on measured actuation \'ohages for real dcviccs. The analysis can provide quick evaluation and screenings of proposed designs to dctcnnine if their actuation voltage falls in the acceptable range. Simulation prediction agrees ver?. well with test measurements. Although increasing cantilever thickncss and shortening cantilever length both increasc restoring force, the actuation vollage will increase significantly as a result. The most favorable moditication is to increase the clcctrode area. A short and wide smctnre with a large area can increase rcstoring force while maintaining low actuation voltage. Compared to similar bi-layer designs, sandwich designs can be actuated at fulther reduced voltages without changing the beam restoring force. In addition, the sandwich structure: being thermal-stress-balanced, is less sensitive to temperature excursion. With the properly selected design parameters, the new designs will be able to achieve the break awav restoring force of the original design at much lower actuation voltages. Switches with good electrical as well as mechanical performances have been successfully fabricated.

A mechanical approach to overcome RF MEMS switch stiction problem

The RF community has long been searching for the ideal switch since the birth of electronics, and it is defined as a device having virtually no insertion loss (Ron = 0 Ω) over a wide frequency range, very high isolation [off-state capacitance (Coff)] = 0 fF), extremely high linearity (IIP2 and IIP3 → infinite), medium- to high-power handling (100 mW to 1 kW), and no dc power consumption. Our entire RF infrastructure ecosystem, from communication system networks, to satellite systems, to wideband spectral analysis, to instrumentation and radar systems, uses a variety of switches for signal routing and control (attenuation, phase shifting, etc.). The ideal switch was achieved long time ago using electromechanical relays, and even after nearly 100 years, it is still the best RF switch ever made from an electrical perspective [1]. It has very low insertion loss (Ron <;1 Ω), very high isolation (Coff of few fF), very high linearity and high power handling (100 mW to 50 W). However, it is bulky, expensive, and has an average lifetime of few million cycles.

The Search for a Reliable MEMS Switch

Chip-packaging interaction: a critical concern for Cu/low k packaging

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.

Impact of flip-chip packaging on copper/low-k structures

It is essential to understand the impact of packaging on chips with copper/low k structures. In this paper, a multi-level, multi-scale modeling technique is used to study the die attach process. Four-level models are built to analyze the packaging impact on the wafer-level behavior. An interface fracture mechanics-based approach is adopted to predict interface delamination. The impact of thin film residual stresses is studied at both the wafer level and package level. Both Plastic Ball Grid Array (PBGA) and Ceramic Ball Grid Array (CBGA) packages are evaluated. Critical failure locations and interfaces are identified for both packages. Two solutions are suggested to prevent catastrophic delamination in copper low-k flip-chip packages.

A simulation method for predicting packaging mechanical reliability with low /spl kappa/ dielectrics

Motorola Semiconductor Products Sector (SPS) has made significant progress in developing an integrated MEMS switch network for use in next-generation portable wireless systems. This MEMS switch technology has significantly better RF characteristics than conventional PIN diodes or FET switches and consumes less power. The RF MEMS switch exhibits insertion loss under 0.3 dB, isolation greater than 50 dB, and operating power under 200 /spl mu/W. The RF MEMS switch chip is integrated with a high voltage charge pump plus control logic chips into a single package that provides a network system to accommodate low voltage requirements in portable wireless applications.

Motorola MEMS switch technology for high frequency applications

In discrete radio frequency (RF) microelectromechanical systems (MEMS) packages, MEMS devices were fabricated on silicon or gallium arsenide (GaAs) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 /spl Omega/ exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities. In this paper, thermal analysis has been performed to study the heat dissipation at the switch contact area. The goal is to control the "hot spots" and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials has been considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and low-temperature cofired ceramic (LTCC) have been studied. Thermal experiments have been conducted to measure the temperature at the contact area and its vicinity as a function of dc and RF powers. Several solutions in material selection and package configurations have been explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity. For discrete MEMS packages, placing the die inside a copper cavity on the substrate provides significant heat dissipation. For wafer-level packages, thin diamond coatings on the substrate could reduce the hot-spot temperature considerably.

Thermal solutions for discrete and wafer-level RF MEMS switch packages

RF MEMS switches offer significant performance advantages in high frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320°C. The assembled packages were then attached to a printed circuit board at 220°C. During the process, some switches failed due to electrical shorting. More interestingly, more failures were observed at the lower temperature of 220°C rather than 320°C. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance.© 2002 ASME

Shun-Meen Kuo

Papers

Impact of flip-chip packaging on copper/low-k structures

A simulation method for predicting packaging mechanical reliability with low /spl kappa/ dielectrics

Motorola MEMS switch technology for high frequency applications

Thermal solutions for discrete and wafer-level RF MEMS switch packages

Process-Induced Thermal Effect on Packaging Yield of RF MEMS Switches