Ion implantation for isolation of III-V semiconductors

Publisher Summary This chapter provides an overview of the new techniques for fabrication at a size scale below 100 nm. A number of nanometer-scale devices and scientific studies have become possible with these techniques, and research in this field has seen a number of recent successes. The chapter focuses on the limits and applications of the nanometer-scale fabrication techniques, not their practicality for current device production. The chapter presents the three-dimensional techniques that seem to permit fabrication of structures smaller than 10 nm. However, there are a variety of effects that limit their resolution. The most obvious is penumbra because of limited collimation of the ion beam or evaporant flux. This effect can be eliminated at the cost of reduced flux by simply using apertures or moving the source further from the sample. The chapter also describes the utilization of the third dimension and new three-dimensional lithographic approaches. Such approaches are of clear advantage for achieving high-aspect-ratio patterns, high resolution, and good line width control over a large field of view. When three-dimensional approaches are combined with other self-aligning or self-limiting processes, very powerful device micro-fabrication approaches can be developed.

Chapter 4 - Nanometer-Scale Fabrication Techniques

Applications of focused ion beams

Focused ion beam milling

Damage formation and annealing of ion implantation in Si

Focused ion beams from Au–Si, Au–Be, and B–Pt liquid–metal–alloy ion sources have been used to implant GaAs and Si. An Al stopping layer on the wafers was used to trap the Au and Pt ions. Hall mobilities consistent with those in bulk materials have been obtained for B‐doped Si and Be‐doped GaAs. In addition, a 2000‐A‐diam Au–Si focused ion beam was used to implant the doped regions of GaAs metal‐semiconductor gate field‐effect transistors. The 140‐keV Si++ beam component was deflected under computer control to implant 8×50 μm active channel regions and 16×50 μm contact regions. The devices were metalized using conventional lithography. DC electrical characteristics of the 1.5‐μm‐gate‐length devices are comparable to those of conventionally processed devices of identical geometry.

FET fabrication using maskless ion implantation

The lattice disorder produced in Si by a 59‐keV Ga+ ion beam focused to a diameter of 1200 A and having a current density of 1.2 A/cm2 was compared to that produced by broad area implantations of 59‐keV Ga+ at a current density of 0.4 μA/cm2. Based on 140‐keV proton backscattering, the disorder produced at the high‐dose rate was found to be comparable although deeper than that produced by the low‐dose‐rate implantations. The depth profile of Ga implanted at 1.2 A/cm2 to a dose of 1.5×1015/cm2 was determined by 280‐keV He++ backscattering to be basically consistent with projected range calculations.

High current density Ga+ implantations into Si

A 2000-A-diameter focused-ion beam from a Au-Si liquid-metal-alloy ion source was used to implant the doped regions of GaAs metal-semiconductor gate field-effect transistors. An Al stopping layer on the wafer was used to trap the Au ions. The 140-keV Si++beam component was deflected under computer control to implant 8 × 50 µm active channel regions and 16 × 50 µm contact regions. The devices were metallized using conventional lithography. DC electrical characteristics of the 1.5-µm-gate-length devices are comparable to those of conventionally processed devices of identical geometry.

C.L. Anderson

Papers

FET fabrication using maskless ion implantation

High current density Ga+ implantations into Si

GaAs MESFET fabrication using maskless ion implantation