Introduction to systems general properties of linear systems the geometric approach - analysis, synthesis, robustness optimality.

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Controlled and conditioned invariants in linear system theory

A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful criterion. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25-/spl mu/m IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect.

Figures of merit to characterize the importance of on-chip inductance

On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits.

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Exploiting the on-chip inductance in high-speed clock distribution networks

The local testability problem of deterministic finite automata is investigated. A locally testable language is a language with the property that, for some nonnegative integer k, whether or not a word w is in the language depends on (1) the prefix and suffix of w of length k, and (2) the set of substrings of w length k+1, without regard to the order in which these substrings occur. The local testability problem is, given a deterministic finite automation, to decide whether or not it accepts a locally testable language. The authors present an O(n/sup 2/) time algorithm for the local testability problem based on two simple properties that characterize locally testable automata. >

A polynomial time algorithm for the local testability problem of deterministic finite automata

Bounded uncorrelated jitter (BUJ), a subcomponent of total jitter, is commonly caused by crosstalk coupling from adjacent interconnects on printed circuit boards (PCB). However, the characteristics of BUJ are still not well understood. Neither a mathematical model of jitter, nor an algorithm to generate histograms for BUJ has been developed to this date. Such a model and algorithm would empower designers to predict BUJ to achieve total jitter budget without lengthy simulations and measurements. In this paper, we first review the characteristics of a crosstalk pulse induced by an aggressor signal on a quiet trace. Then, by applying the superposition principle, a jitter model to calculate the time difference between the distortion-free and the distorted edge crossings of the victim signal was developed. This model is also extended to calculate the worst case timing difference, BUJ/sub p-p/. In addition, an algorithm to generate the histogram distribution of BUJ is also developed. The developed algorithm has fast execution times of 10-20 s, compared to simulation and measurement times of 10-30 min.

Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects

A kth-order finite automaton is an automaton whose next state is a function of its most recent k states as well as its present input. A procedure to test whether a given ordinary automaton is equivalent to some kth-order automaton is suggested.

kth-Order Finite Automaton

Methods are developed to illustrate whether or not it is possible to determine the final state of a finite automaton when 1) the initial state of the automaton is unknown and the input sequence and its corresponding output sequence are given and 2) both the initial state and the input sequence are unknown and only the output sequence is given.

C. L. Liu

Papers

kth-Order Finite Automaton

Determination of the Final State of an Automaton Whose Initial State Is Unknown

Some algebraic properties of multi-threshold functions