The operation-centric hardware abstraction is useful for describing systems whose behavior exhibits a high degree of concurrency. In the operation-centric style, the behavior of a system is described as a collection of operations on a set of state elements. Each operation is specified as a predicate and a set of simultaneous state-element updates, which may only take effect in case the predicate is true on the current state values. The effect of an operation's state updates is atomic, that is, the legal behaviors of the system constitute some sequential interleaving of the operations. This atomic and sequential execution semantics permits each operation to be formulated as if the rest of the system were frozen and thus simplifies the description of concurrent systems. This paper presents an approach to synthesize an efficient synchronous digital implementation from an operation-centric hardware-design description. The resulting implementation carries out multiple operations per clock cycle and yet maintains the semantics that is consistent with the atomic and sequential execution of operations. The paper defines, and then gives algorithms to identify, conflict-free and sequentially composable operations that can be performed in the same clock cycle. The paper further gives an algorithm to generate the hardwired arbitration logic to coordinate the concurrent execution of conflict-free and sequentially composable operations. Lastly, the paper evaluates synthesis results based on the TRAC compiler for the TRSPEC operation-centric hardware-description language. The results from a pipelined processor example show that an operation-centric framework offers a significant reduction in design time, while achieving comparable implementation quality as traditional register-transfer-level design flows.

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Operation-centric hardware description and synthesis

Current processors are programmed through a fixed interface called the Instruction Set Architecture (ISA). Consequently, a compiler targeting such a processor is forced to choose instructions from the provided instruction set. Often this instruction set is not a suitable match for the computational requirements of the application program. With in this context, we ask ourselves the following questions. (1) Can application performance be improved if the compiler had the freedom to wick the instruction set on a per application basis? (2) Can we build cost-effective processors that provide the ability to efficiently emulate compiler determined instruction sets and yet are not application specific? (3) Given that the desired processor capabilities are feasible, can the compiler determine an optimal set of instructions for a given application and generate code that can effectively exploit the processor capabilities? 
In this thesis, we provide sufficient evidence to answer these questions in the affirmative. Through a combination of architectural innovations and novel compilation techniques, this dissertation demonstrates that it is possible to attain significant improvement in performance, on general purpose and multimedia applications over comparable fixed ISA processors. 
First half of this dissertation describes this novel class of architectures, focusing on a specific subclass called Adaptive Explicitly Parallel Instruction Computing (ASPIC) architectures whose definition represents a collection of ideas intended to enable efficient reconfiguration of processor data paths. While ASPIC processor reconfiguration is affected by the executing program at runtime, the decisions of when and how to reconfigure are determined by the compiler and embedded in the application's executable. 
In the second half, a compilation framework targeting ASPIC processors is proposed. Several key compilation problems that need to be addressed in order to target ASPIC processors such as partitioning, instruction synthesis, configuration selection, resource allocation and scheduling are defined and efficient techniques for solving them are proposed. 
Finally, we describe the design of a simulation and performance monitoring framework for ASPIC architectures. How such architectures can be used to improve application performance is demonstrated using a set of programs from the SPEC and MediaBench benchmarks. Experimental results indicate the significant role architectural features of ASPIC processors play in masking the overheads of micro-architectural reconfiguration.

Adaptive explicitly parallel instruction computing

This paper presents a transactional specification framework (T-spec) for describing a datapath and the tool T-piper to synthesize automatically an in-order pipelined implementation with arbitrary user-specified pipeline-stage boundaries. T-spec abstractly views a datapath as executing one transaction at a time, computing the next system states based on the current ones. The synthesized pipeline maintains this semantics, yet allows concurrent execution of multiple overlapped transactions in different pipeline stages, where each stage performs a part of the next-state computation of each transaction. T-spec makes the state reading and writing events in a datapath explicit to enable T-piper to perform exact read-after-write (RAW) hazard analysis between the overlapped transactions. T-piper can automatically generate the pipeline control not only to ensure the correctness of the pipelined executions but also to minimize (using forwarding and speculation) the performance loss due to pipeline stalls in the presence of RAW dependencies. This paper reports design case studies applying T-spec and T-piper to reduced instruction set computing and complex instruction set computing processor pipeline development. In the latter, we report the results from a rapid design space exploration of 60 generated x86-subset pipelines, varying in pipeline depth, forwarding, and speculative execution, all starting from a single T-spec.

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Automatic Pipelining From Transactional Datapath Specifications

In this approach, the logic is restructured using an intermediate placement solution and then the placement is adjusted to match the new logic structure. This ability to change logic structure during layout allows one to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing. Parts on an industrial chip have been resynthesized using a prototype program implementing these ideas with an average of 11.2% reduction in bit slice area compared to the original designs. >

Alleviating routing congestion by combining logic resynthesis and linear placement

The authors propose a synthesis methodology for high-performance pipelined instruction set processors. Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of the Advanced Design Automation System (ADAS) which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is to perform pipeline scheduling with any fixed instruction-latency, and generate a reorder table for a back-end compiler to resolve potential pipeline hazards existing in the design. Models for performance and cost of both hardware and software are developed to characterize the design space. A synthesis example of a simple instruction set processor illustrates Piper's synthesis capabilities and how the performance and cost of hardware and software are estimated. >

High level synthesis of pipelined instruction set processors and back-end compilers

The authors present an overview of the application-driven design automation system (ADAS) for microprocessor design. ADAS accepts a specification of the instruction set architecture as input, and produces both layout specified in Caltech Intermediate Form, and a reorder table for the language compiler as output. The system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation. Another goal of the project is to determine the feasibility of applying formal methodology to design automation and the usefulness of formal syntax and semantics in defining the meaning of specifications. The system implementation on a real industrial example, the TDY-43 processor, is discussed. >

C. L. Su

Papers

Application-driven design automation for microprocessor design