: A given switching function of n variables can frequently be decomposed into a composite function of several essentially simpler switching functions. Such decompositions lead to designs of more economical switching circuits to realize the given switching function. Ashenhurst's chart method is generalized to nondisjunctive decompositions by means of the don't care conditions. This extension provides an effective method of constructing all decompositions of switching functions. (Author)

On the decomposition of switching functions

This paper proposes a new approach to multi-level logic optimization based on ATPG (Automatic Test Pattern Generation). Previous ATPG-based methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. We show that the ATPG-based method presented here allows (in principle) the transformation of a given combinational network C into an arbitrary, structurally different but functionally equivalent combinational network C'. Furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good” candidates for the minimization of the circuit. In particular, it is shown that Recursive Learning can derive “good” Boolean divisors justifying the effort to attempt a Boolean division. For 9 out of 10 ISCAS-85 benchmark circuits our tool HANNIBAL obtains smaller circuits than the well-known synthesis system SIS.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1994/iccad94/pdffiles/01a_2.pdf

Multi-level logic optimization by implication analysis

The operation-centric hardware abstraction is useful for describing systems whose behavior exhibits a high degree of concurrency. In the operation-centric style, the behavior of a system is described as a collection of operations on a set of state elements. Each operation is specified as a predicate and a set of simultaneous state-element updates, which may only take effect in case the predicate is true on the current state values. The effect of an operation's state updates is atomic, that is, the legal behaviors of the system constitute some sequential interleaving of the operations. This atomic and sequential execution semantics permits each operation to be formulated as if the rest of the system were frozen and thus simplifies the description of concurrent systems. This paper presents an approach to synthesize an efficient synchronous digital implementation from an operation-centric hardware-design description. The resulting implementation carries out multiple operations per clock cycle and yet maintains the semantics that is consistent with the atomic and sequential execution of operations. The paper defines, and then gives algorithms to identify, conflict-free and sequentially composable operations that can be performed in the same clock cycle. The paper further gives an algorithm to generate the hardwired arbitration logic to coordinate the concurrent execution of conflict-free and sequentially composable operations. Lastly, the paper evaluates synthesis results based on the TRAC compiler for the TRSPEC operation-centric hardware-description language. The results from a pipelined processor example show that an operation-centric framework offers a significant reduction in design time, while achieving comparable implementation quality as traditional register-transfer-level design flows.

/pdf/operation-centric-hardware-description-and-synthesis-guzguku502.pdf

Operation-centric hardware description and synthesis

In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a CAD tool perspective are surveyed, and methodologies and directions are proposed for the next generation design automation tools, intended to meet the challenges ahead. Ideas such as forward synthesis, incremental synthesis, system-level interconnect prediction and planning, and their implications on design quality design tool architecture, and design methodology are explored.

Quality of EDA CAD tools: definitions, metrics and directions

In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations are integrated into the placement process, an accurate net delay model is available. This model provides the basis for e ective netlist transformations. In contrast to previous approaches that apply netlist transformations during placement, we are not restricted to local transformations like fanout bu ering or gate resizing. Instead, we exploit global dependencies between the signals in the circuit. Results for benchmark circuits show excellent placement quality. The maximum path delay is reduced up to 33% compared to the initial timing driven placement of the original netlist and up to 18% compared to the results obtained by consecutive optimization of the netlist and timing driven placement of the optimized netlist. This delay reduction is achieved with almost no increase in chip area.

Timing driven placement in interaction with netlist transformations

In this approach, the logic is restructured using an intermediate placement solution and then the placement is adjusted to match the new logic structure. This ability to change logic structure during layout allows one to obtain channel density reductions that are not possible by physical design operations such as lateral shifting, pin permutation, and channel routing. Parts on an industrial chip have been resynthesized using a prototype program implementing these ideas with an average of 11.2% reduction in bit slice area compared to the original designs. >

Alleviating routing congestion by combining logic resynthesis and linear placement

The authors present an overview of the application-driven design automation system (ADAS) for microprocessor design. ADAS accepts a specification of the instruction set architecture as input, and produces both layout specified in Caltech Intermediate Form, and a reorder table for the language compiler as output. The system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation. Another goal of the project is to determine the feasibility of applying formal methodology to design automation and the usefulness of formal syntax and semantics in defining the meaning of specifications. The system implementation on a real industrial example, the TDY-43 processor, is discussed. >

Application-driven design automation for microprocessor design

This paper addresses the problem of state assignment for large Finite State Machines (FSM). This is an important problem in the high performance digital system design where added functionality often comes at the expense of a larger (and slower) FSM to control the system. We present a new method to solve the graph embedding problem which is the main step in the state assignment process. The basic idea is to place the state adjacency graph in a two-dimensional grid while minimizing the total wire length. The grid is then mapped into an n-dimensional hypercube while nearly preserving the adjacency relations that is with dilation at most 2. Experimental results are presented and compared with those of NOVA.

A Fast State Assignment Procedure for Large FSMs

This paper addresses the problem of partitioning a large PLA into a number of smaller PLA's (sub-PLA's) such that the total area of these sub-PLA's is minimum and the cycle time of the partitioned circuit is minimized. First, we describe an iterative improvement method that deals with the case that sub-PLA's assume arbitrary sizes. Second, we present a partitioning technique based on fuzzy logic that deals with the case that the sizes of the sub-PLA's are fixed. Finally, we describe a method that considers not only delay through each sub-PLA, but also loading of sub-PLA's on the stage that is driving them. These techniques have been implemented and significantly outperformed conventional PLA partitioning schemes.

S. Liu

Papers

Alleviating routing congestion by combining logic resynthesis and linear placement

Application-driven design automation for microprocessor design

A Fast State Assignment Procedure for Large FSMs

PLATO P: PLA timing optimization by partitioning

State assignment based on two-dimensional placement and hypercube mapping